MC9S08DZ128 Datasheet, PDF (177/458 Pages) Freescale Semiconductor, Inc – Microcontrollers

8.3.6
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
MCG Test and Control Register (MCGT)
7
R
0
W
Reset:
0
6
5
4
3
2
0
0
0
0
DMX32
0
0
0
0
0
Figure 8-8. MCG Test and Control Register (MCGT)
1
0
0
DRST
DRS
0
1
dco_select
Table 8-8. MCG Test and Control Register Field Descriptions
Field
7:6
5
DMX32
4:1
0
DRST
DRS
Description
Reserved for test, user code should not write 1’s to these bits.
DCO Maximum frequency with 32.768 kHz reference — The DMX32 bit controls whether or not the DCO
frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. See Table 8-9.
0 DCO has default range of 25%.
1 DCO is fined tuned for maximum frequency with 32.768 kHz reference.
Reserved for test, user code should not write 1’s to these bits.
DCO Range Status — The DRST read bit indicates the current frequency range for the FLL output, DCOOUT.
See Table 8-9. The DRST bit does not update immediately after a write to the DRS field due to internal
synchronization between clock domains. The DRST bit is not valid in BLPI, BLPE, PBE or PEE mode and it reads
zero regardless of the DCO range selected by the DRS bit.
DCO Range Select — The DRS bit selects the frequency range for the FLL output, DCOOUT. Writes to the DRS
bit while either the LP or PLLS bit is set are ignored.
0 Low range.
1 Mid range.
Table 8-9. DCO frequency range¹
DRS DMX32 Reference range
FLL factor
DCO range
0 31.25 - 39.0625 kHz
512
0
1
32.768 kHz
608
16 - 20 MHz
19.92 MHz
0 31.25 - 39.0625 kHz
1
1
32.768 kHz
1024
1216
32 - 40 MHz
39.85 MHz
1 _{The resulting bus clock frequency should not exceed the maximum specified bus}
clock frequency of the device.
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
177