XRT7250 Datasheet, PDF (99/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

XRT7250 DS3/E3 FRAMER IC
REV. 1.1.1
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RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
COFA
Interrupt
Enable
OOF
Interrupt
Enable
RO
RO
RO
R/W
R/W
0
0
0
0
0
BIT 2
LOF
Interrupt
Enable
R/W
0
BIT 1
LOS
Interrupt
Enable
R/W
0
BIT 0
AIS
Interrupt
Enable
R/W
0
Bit 4 - COFA (Change of Frame Alignment) Inter-
rupt Enable
This Read/Write bit-field allows the user to enable or
disable the Change of Frame Alignment interrupt.
Setting this bit-field to "1" enables this interrupt. Set-
ting this bit-field to "0" disables this interrupt.
Bit 3 - OOF (Change in OOF Condition) Interrupt
Enable
This Read/Write bit field allows the user to enable or
disable the Change in Out-of-Frame (OOF) status in-
terrupt. Setting this bit-field to "1" enables this inter-
rupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the OOF Condition, please
see Section 4.3.2.2.
Bit 2 - LOF (Change in LOF Condition) Interrupt
Enable
This Read/Write bit-field allows the user to enable or
disable the Change in Loss-of-Frame (LOF) status in-
terrupt. Setting this bit-field to "1" enables this inter-
rupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the LOF Condition, please
see Section 4.3.2.2.
Bit 1 - LOS (Change in LOS Condition) Interrupt
Enable
This Read/Write bit-field allows the user to enable or
disable the Change in LOS condition interrupt. Set-
ting this bit-field to "1" enables this interrupt. Setting
this bit-field to "0" disables this interrupt.
NOTE: For more information on the LOS Condition, please
see Section 4.3.2.7.
Bit 0 - AIS (Change in AIS Condition) Interrupt En-
able
This Read/Write bit-field allows the user to enable or
disable the Change in AIS condition interrupt. Setting
this bit-field to "1" enables this interrupt. Setting this
bit-field to "0" disables this interrupt.
NOTE: For more information on the AIS Condition, please
see Section 4.3.2.8
2.3.4.4 Receive E3 Interrupt Enable Register -
2 (E3, ITU-T G.751)
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
FERF
Interrupt
Enable
R/W
RO
RO
RO
R/W
0
0
0
0
0
BIT 2
BIT 1
BIP-4 Error Framing Error
Interrupt
Interrupt
Enable
Enable
R/W
R/W
0
0
BIT 0
Not Used
RO
0
Bit 3 - FERF (Far-End Receive Failure) Interrupt
Enable
This Read/Write bit-field allows the user to enable or
disable the Change in FERF Condition interrupt. Set-
ting this bit-field to "1" enables this interrupt. Setting
this bit-field to "0" disables this interrupt.
NOTE: For more information on the Change in FERF Condi-
tion interrupt, please see Section 4.3.6.1.6.
Bit 2 - BIP-4 Error Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the BIP-4 Error interrupt. Setting this bit-field
to "1" enables this interrupt. Setting this bit-field to
"0" disables this interrupt.
NOTE: For more information on this interrupt, please see
Section 4.3.6.1.7.
Bit 1 - Framing Error Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Framing Error interrupt. Setting this bit-
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