XRT7250 Datasheet, PDF (139/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

XRT7250 DS3/E3 FRAMER IC
REV. 1.1.1
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TABLE 13: INTERRUPT SERVICE ROUTINE LOCATION (IN CODE MEMORY) FOR THE INT0* AND INT1* INTERRUPT
INPUT PINS
INTERRUPT PIN
BRANCH TO LOCATION (IN SYSTEM MEMORY)
INT0*
0x0003
INT1*
0x0013
Therefore, if the user is using either one of these in-
puts as an interrupt request input, then the user must
ensure that the appropriate interrupt service routine
or unconditional branch instruction (to the interrupt
service routine) is located at one of these address lo-
cations.
If the 8051 Microcontroller IC is required to interface
to external components in the data memory space of
sizes greater than 256 bytes, then both Ports 0 and 2
must be used as the address and data lines. Port 0
will function as a multiplexed address/data bus. Dur-
ing the first half of a memory cycle, Port 0 will operate
as the lower address byte. During the second half of
the memory cycle, Port 0 will operate as the bi-direc-
tional data bus. Port 2 will be used as the upper ad-
dress byte. ALE and the use of a 74HC373 transpar-
ent latch device can be used to de-multiplex the Ad-
dress and Data bus signals.
Figure 37 presents a schematic illustrating how the
XRT7250 DS3/E3 Framer can be interfaced to the
8051 Microcontroller IC.
FIGURE 37. SCHEMATIC DEPICTING HOW TO INTERFACE THE XRT7250 DS3/E3 FRAMER IC TO THE 8051 MICRO-
CONTROLLER
U2
8051
WR
RD
16
17
AD0
AD1
AD2
AD3
39
38
37
36
35
AD4
AD5
AD6
AD7
34
33
32
+5V
INT0
INT1
12
13
30
ALE
21
A8 ₂₂
A9 ₂₃
A10
A11
A12
A13
A14
24
25
26
27
28
A15
RESET Command Circuitry
ALE
INTERRUPT
ALE
U?
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
1
11
OC
G
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
74HC373
INTERRUPT
to Address Decoder
from Address Decoder
U1
28
7
29
RESET
WRB_RW
RDB_DS
32
33
34
35
D0
D1
D2
36
37
38
39
D3
D4
D5
D6
D7
31 _{ALE_AS}
14
15
16
17
18
19
20
21
22
A0
A1
A2
A3
A4
A5
A6
A7
A8
6
Rdy_Dtck
13
INT
8 _CS
27
MOTO/INTEL
XRT7250
The circuitry in Figure 37 will function as follows, dur-
ing a Framer-request interrupt. The Framer device
would request an interrupt from the CPU by asserting
its active low INT output pin. This will cause the
INT0* input pin of the CPU to go "Low”. When this
happens the 8051 CPU will finish executing its cur-
rent instruction, and will then branch program control
to the Framer Device interrupt service routine. In the
case of Figure 37, the interrupt service routine will be
located in 0x0003 in code memory. The 8051 CPU
120