XRT7250 Datasheet, PDF (66/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

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DS3/E3 FRAMER IC
XRT7250
REV. 1.1.1
illustrate this point, the byte (or word) of data, that is
being written in Figure 31 has been labeled Data to
be Written (Offset = 0x00).
2.2.2.2.1.2.2 The Subsequent Write Operations
The procedure that the µC/µP must use to perform
the remaining write cycles, within this burst access
operation, is presented below.
B.0 Execute each subsequent write cycle, as
described in steps B.1 through B.3.
B.1 Without toggling the ALE_AS input pin (e.g.,
keeping it "Low"), apply the value of the next
byte or word (to be written into the Framer) to
the bi-directional data bus pins, D[7:0].
B.2 Toggle the WR_RW (Write Strobe) input pin
"Low". This step accomplishes two things.
a. It enables the input drivers of the bi-directional
data bus.
b. It causes the Framer to internally increment the
value of the latched address.
B.3 After waiting the appropriate amount of settling
time the data, in the internal data bus, will stabi-
lize and is ready to be latched into the Framer
Microprocessor Interface block. At this point,
the µC/µP should latch the data into the Framer
by toggling the WR_RW input pin "High".
For subsequent write operations, within this burst I/O
access, the µC/µP simply repeats steps B.1 through
B.3, as illustrated in Figure 32.
FIGURE 32. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING SUBSEQUENT WRITE OPERATIONS
WITHIN THE BURST I/O CYCLE
ALE_AS
A[8:0]
CS
D[15:0]
WR_RW
RD_DS
RDY_DTCK
Address of “Initial” Target Register (Offset = 0x00)
Data Written at Offset =0x01
Data Written at Offset =0x02
2.2.2.2.1.2.3 Terminating the Burst I/O Access
Burst Access Operation will be terminated upon the
rising edge of the ALE_AS input signal. At this point
the Framer will cease to internally increment the
latched address value. Further, the µC/µP is now free
to execute either a Programmed I/O access or to start
another Burst Access Operation with the XRT7250
DS3/E3 Framer.
2.2.2.2.2 Burst I/O Access in the Motorola
Mode
If the XRT7250 DS3/E3 Framer is interfaced to a Mo-
torola-type µC/µP (e.g., the MC680x0 family, etc.),
then it should be configured to operate in the Motoro-
la mode (by tying the MOTO pin to VCC). Motorola-
type Read and Write Burst I/O Access operations are
described below.
2.2.2.2.2.1 The Motorola-Mode Read Burst I/O
Access Operation
Whenever a Motorola-type µC/µP wishes to read the
contents of numerous registers or buffer locations
over a contiguous range of addresses, then it should
do the following.
a. Perform the initial Read operation of the burst
access.
b. Perform the remaining read operations in the
burst access.
c. Terminate the burst access operation.
Each of these operations, within the Burst Access are
discussed below.
2.2.2.2.2.1.1 The Initial Read Operation
The initial read operation of a Motorola-type read
burst access is accomplished by executing a Pro-
grammed I/O Read cycle, as summarized below.
A.0 Execute a Single Ordinary (Programmed I/
O) Read Cycle, as described in steps A.1
through A.8 below.
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