XRT7250 Datasheet, PDF (87/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

XRT7250 DS3/E3 FRAMER IC
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REV. 1.1.1
Payload Type value (within the MA Byte-Field) in the
last 5 consecutive incoming E3 frames.
If the Receive E3 Framer has detected a change in
the Payload Type value, within the last 5 incoming E3
frames, then it will set this bit-field to "1". If the Pay-
load Type value has been consistent in the last 5 E3
frames, then the Receive E3 Framer will set this bit-
field to "0".
Bit 1 - Rx TMark
This Read-Only bit-field reflects the most recently val-
idated Timing Marker value. The Receive E3 Framer
will validate the Timing Marker state, after it has de-
tected a user-selectable number of consecutive in-
coming E3 frames with a consistent Timing Marker
value. The user makes this selection by writing the
appropriate value to Bit 3 (RxTMarkAlgo) within the
Rx E3 Configuration/Status Register (Address =
0x0E).
Bit 0 - RxFERF (Far End Receive Failure)
This Read-Only bit-field indicates whether or not the
Receive E3 Framer is experiencing an FERF (Far-
End-Receive-Failure) condition. The Receive E3
Framer will declare a FERF condition, if it has re-
ceived a user-selectable number of consecutive E3
frames, with the FERF bit-field (within the MA byte)
set to "1". This user-selectable number is either 3 or
5 E3 frames. Conversely, the Receive E3 Framer will
negate the FERF declaration, if it has received this
user-selectable number of consecutive E3 frames,
with the FERF bit-field set to "0".
If this bit-field is set to "1", then the Receive E3 Fram-
er has declared an FERF condition. If this bit-field is
set to "0", then the Receive E3 Framer has not de-
clared an FERF condition.
NOTE: Please see Section 5.1.1.4, for a more detailed dis-
cussion on the meaning of the FERF bit-field, within the E3
frame.
2.3.3.3 3.3.2.17 Receive E3 Interrupt Enable
Register (E3, ITU-T G.832)
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Enable
OOF
Interrupt
Enable
LOF
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 4 - Change of Frame Alignment (COFA) Inter-
rupt Enable
This Read/Write bit-field allows the user to enable or
disable the Change of Frame Alignment interrupt.
Setting this bit-field to "1" enables this interrupt. Set-
ting this bit-field to "0" disables this interrupt.
Bit 3 - OOF (Out of Frame) Interrupt Enable
This Read/Write bit field allows the user to enable or
disable the Change in Out-of-Frame (OOF) status in-
terrupt. Setting this bit-field to "1" enables this inter-
rupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the OOF Condition, please
see Section 5.3.2.1.
Bit 2 - LOF (Loss of Frame) Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Change in Loss-of-Frame (LOF) status in-
terrupt. Setting this bit-field to "1" enables this inter-
rupt. Setting this bit-field to "0" disables this interrupt.
For more information on the LOF Condition, please
see Section 5.3.2.1.
Bit 1 - LOS (Loss of Signal) Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Change in LOS condition interrupt. Set-
ting this bit-field to "1" enables this interrupt. Setting
this bit-field to "0" disables this interrupt.
NOTE: For more information on the LOS Condition, please
see Section 5.3.2.6.
Bit 0 - AIS Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Change in AIS condition interrupt. Setting
this bit-field to "1" enables this interrupt. Setting this
bit-field to "0" disables this interrupt.
NOTE: For more information on the AIS Condition, please
see Section 5.3.2.6.2.
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