XRT7250 Datasheet, PDF (123/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

XRT7250 DS3/E3 FRAMER IC
REV. 1.1.1
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TXE3 FAS ERROR MASK REGISTER - 1 (ADDRESS = 0X49)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Not Used
TxFAS_Error_Mask_Lower[4:0]
RO
RO
RO
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
BIT 0
R/W
0
Bits 4 - 0, TxFAS_Error_Mask_Lower[4:0]
This Read/Write bit-field permits the user to insert er-
rors into the lower five bits of the Framing Alignment
Signal, FAS of each outbound E3 frame. The user
may wish to do this for equipment testing purposes.
Prior to transmission, the Transmit E3 Framer block
reads in the lower five (5) bits of the FAS value, and
performs an XOR operation with it and the contents of
this register. The results of this operation are written
back into the lower five (5) bits of the FAS value, in
each outbound E3 frame. Consequently, to insure er-
rors are not injected into the FAS of the outbound E3
frames, the contents of this register must be set to all
"0’s" (the default value).
2.3.7.7 Transmit E3 BIP-4 Error Mask Register
(ITU-T G.751)
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
TxBIP-4 Mask[3:0]
R/W
R/W
0
0
BIT 0
R/W
0
Bits 3 - 0: TxBIP-4 Mask[3:0]
This Read/Write bit-field permits the user to insert er-
rors into the BIP-4 value within each outbound E3
frame. The user may wish to do this for equipment
testing purposes. Prior to transmission, the Transmit
E3 Framer reads in the BIP-4 value, and performs an
XOR operation with it and the contents of this regis-
ter. The results of this operation are written back into
the BIP-4 nibble position, in each outbound E3 frame.
Consequently, to insure errors are not injected into
the BIP-4 value of the outbound E3 frames, the con-
tents of this register must be set to all "0’s" (the de-
fault value).
2.3.8 Performance Monitor Registers
2.3.8.1 PMON Line Code Violation Count Reg-
ister - MSB
PMON LCV EVENT COUNT REGISTER - MSB (ADDRESS = 0X50)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
LCV Count - High Byte
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
This Reset-upon-Read register, along with the PMON
LCV Event Count Register - LSB (Address = 0x51)
contains a 16-bit representation of the number of Line
Code Violations that have been detected by the Re-
ceive E3 Framer, since the last read of these regis-
ters. This register contains the MSB (or Upper-Byte)
value of this 16 bit expression.
2.3.8.2 PMON Line Code Violation Count Reg-
ister - LSB
104