XRT7250 Datasheet, PDF (97/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

XRT7250 DS3/E3 FRAMER IC
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REV. 1.1.1
This Read-Only register contains the fifteenth (15th)
byte within the 16 byte Trail Trace Buffer Message,
that has been received from the Far-End Terminal.
This register typical contains an ASCII character that
is required for the E.164 numbering format.
NOTE: For more information on the use of this register,
please see Section 5.3.2.9.
2.3.3.26 Receive E3 TTB-15 Register (E3, ITU-T
G.832)
RXE3 TTB-15 REGISTER (ADDRESS = 0X2B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxTTB-15
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
This Read-Only register contains the sixteenth (16th)
byte within the 16 byte Trail Trace Buffer Message,
that has been received from the Far-End Terminal.
This register typical contains an ASCII character that
is required for the E.164 numbering format.
NOTE: For more information on the use of this register,
please see Section 5.3.2.9.
2.3.4 Receive E3 Framer Configuration Regis-
ters (ITU-T G.751)
2.3.4.1 Receive E3 Framer Configuration &
Status Register - 1 (E3, ITU-T G.751)
RXE3 CONFIGURATION & STATUS REGISTER - 1 G.751 (ADDRESS = 0X10)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Reserved
RxFERF
Algo
Reserved
RO
RO
RO
R/W
RO
RO
0
0
0
0
0
0
BIT 1
RO
0
BIT 0
RxBIP4
R/W
0
Bit 4 - RxFERF Algo(rithm) Select
This Read/Write bit-field permits the user to select
the Received FERF Declaration Algorithm.
Setting this bit-field to "0", configures the Receive
Section of the XRT7250 to declare a FERF (Far-End-
Receive Failure), after three (3) consecutive E3
frames, with the A-bit set to "1", have been received.
Further, the Receive Section of the XRT7250 will
clear FERF, after three (3) consecutive E3 frames,
with the A-bit set to "0", have been received.
Setting this bit-field to "1", configures the Receive
Section of the XRT7250 to declare a FERF, after five
(5) consecutive E3 frames, with the A-bit set to "1",
have been received. Further, the Receive Section of
the XRT7250 will clear FERF after five (5) consecu-
tive E3 frames, with the A-bit set to "0", have been re-
ceived.
Bit 0 - RxBIP4 Enable
This Read/Write bit-field permits the user to configure
the Receive Section of the XRT7250 to verify (or not
verify) the BIP-4 value within each incoming E3
frame.
Setting this bit-field to "0", configures the Receive
Section of the XRT7250 to NOT verify the BIP-4 value
within each incoming E3 frame.
Setting this bit-field to "1", configures the Receive
Section of the XRT7250 to verify the BIP-4 value with-
in each incoming E3 frame.
2.3.4.2 Receive E3 Framer Configuration &
Status Register -2 (E3, ITU-T G.751)
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