XRT7250 Datasheet, PDF (140/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

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DS3/E3 FRAMER IC
XRT7250
does not issue an Interrupt Acknowledge signal back
to the Framer IC. It will just begin processing through
the Framer’s interrupt service routine. One the CPU
has eliminated the cause(s) of the interrupt request,
the Framer’s INT output pin will be negated (e.g., go
"High”) and the CPU will return from the Interrupt Ser-
vice Routine and resume normal operation.
REV. 1.1.1
2.8 INTERFACING THE FRAMER IC TO A MOTOROLA-
TYPE MICROPROCESSOR
This section discusses how to interface the XRT7250
DS3/E3 Framer IC to the MC68000 Microprocessor.
Figure 38 presents a schematic on how to interface
the XRT7250 DS3/E3 Framer IC to the MC68000 Mi-
croprocessor, over an 8-bit wide bi-directional data
bus.
FIGURE 38. SCHEMATIC DEPICTING HOW TO INTERFACE THE XRT7250 DS3/E3 FRAMER IC TO THE MC68000
MICROPROCESSOR
U2
MC68000
18
RESET
R/W
9
10
DTACK
5
D0 ₄
D1 ₃
D2
D3
D4
2
1
64
D5 ₆₃
D6
D7
D8
62
61
60
D9 ₅₉
D10 ₅₈
D11
D12
57
56
D13
D14
D15
55
54
25
IPL0
IPL1
IPL2
24
23
21
VPA
FC0
FC1
FC2
28
27
26
AS
UDS
LDS
6
7
8
A1
29
30
A2
A3
31
32
A4
A5
A6
33
34
35
A7 ₃₆
A8
37
A9 ₃₈
A10 ₃₉
A11
A12
40
41
A13
A14
42
43
A15
A16
44
45
A17
A18
46
47
A19
A20
48
49
A21
A22
50
51
A23
D[15:8]
U4
9
7
A0
6 ^A1
A2
14 _GS
0
10
11
1 ₁₂
2 ₁₃
3
4
1
2
5
6
7
3
4
15
5
EO
EI
U6A
74AHCT148
3
1
2
U3
+5V
1
2
3
A
B
C
Y0
Y1
Y2
15
14
13
12
74AHCT00
6
4
5
G1
G2A
Y3
Y4
Y5
Y6
11
10
9
7
G2B
Y7
74AHCT138
Address_Strobe
Data_Strobe
U5
1
2
A
Y0
15
14
+5V
3
B
C
Y1
Y2
13
12
6
Y3
Y4
11
10
4
5
G1
G2A
Y5
Y6
9
7
G2B
Y7
74AHCT138
to Address Decoder
from Address Decoder
Data_Strobe
Address_Strobe
U7B
4
3
74AHCT04
U7A
74AHCT04
U1
28
7
6
RESET
WRB_RW
Rdy_Dtck
32
33 ^D0
34
35
36
D1
D2
D3
37 ^D4
38
39
D5
D6
D7
10
9
RDB_DS
ALE_AS
14
15
16
17
18
A0
A1
A2
A3
19 ^A4
20
21
22
A5
A6
A7
A8
13 _INT
8 _CS
+5V
27
MOTO/INTEL
XRT7250
In general, the approach to interfacing these two de-
vices is pretty straightforward. However, the user
must be aware of the fact that the XRT7250 DS3/E3
Framer IC does not provide an interrupt vector to the
MC68000 during an Interrupt Acknowledge cycle.
Therefore, the user must configure his/her design to
support auto-vectored interrupts. Auto-vectored in-
terrupt processing is a feature offered by the
MC68000 Family of Microprocessors, where, if the
microprocessor knows (prior to any IACK cycle) the
Interrupt Level of this current interrupt, and that the
interrupting peripheral does not support vectored in-
terrupts, then the Microprocessor will generate its
own Interrupt Vector. The schematic shown in
Figure 38, has been configured to support auto-vec-
tored interrupts.
121