XRT7250 Datasheet, PDF (122/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

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DS3/E3 FRAMER IC
XRT7250
REV. 1.1.1
insert flag sequence octets into the outbound LAPD chan-
nel, during the idle periods between transmissions.
Bit 2 - TxDL Busy
This Read-Only bit-field allows the user to poll or
monitor the status of the LAPD Transmitter to see if it
has completed its transmission of the LAPD Message
frame. The LAPD Transmitter will set this bit-field to
"1", while it is in the process of transmitting the LAPD
Message frame. However, the LAPD Transmitter will
clear this bit-field to "0" once it has completed its
transmission of the LAPD Message frame.
Bit 1 - TxLAPD Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the LAPD Message frame Transmission Com-
plete interrupt.
Writing a "0" to this bit-field disables this interrupt.
Writing a "1" to this bit-field enables this interrupt.
Bit 0 - TxLAPD Interrupt Status
This Reset-upon-Read bit-field allows the user to de-
termine if the LAPD Message Frame Transmission
Complete interrupt has occurred since the last read of
this register. If this bit-field contains a "1" then the
LAPD Message Frame Transmission Complete inter-
rupt has occurred since the last read of this register.
Conversely, if this bit-field contains a "0" then it has
not.
2.3.7.4 Transmit E3 Service Bits Register (ITU-
T G.751)
TXE3 SERVICE BITS REGISTER (ADDRESS = 0X35)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
A Bit
N Bit
RO
RO
RO
RO
RO
RO
R/W
R/W
0
0
0
0
0
0
1
0
Bit 1 - A Bit
This Read/Write bit-field permits the user to define
the value of the A Bit within a given outbound E3
frame. If the user has configured the source of the A
Bit to be the TxE3 Service Bits Register (by setting
TxASource[1:0] = 00, within the TxE3 Configuration
Register, Address = 0x30), then the value written in
this bit-field will specify the value of the A Bit within
the outbound E3 Frame.
Bit 0 - N Bit
This Read/Write bit-field permits the user to define
the value of the N Bit within a given outbound E3
frame. If the user has configured the source of the N
Bit to be the TxE3 Service Bits Register (by setting
TxNSource[1:0] = 00, within the TxE3 Configuration
Register, Address = 0x30), then the value written in
this bit-field will specify the value of the N Bit within
the outbound E3 Frame.
2.3.7.5 Transmit E3 FAS Mask Register - 0
(ITU-T G.751)
TXE3 FAS ERROR MASK REGISTER - 0 (ADDRESS = 0X48)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
R/W
0
BIT 3
BIT 2
BIT 1
TxFAS_Error_Mask_Upper[4:0]
R/W
R/W
R/W
0
0
0
BIT 0
R/W
0
Bits 4 - 0, TxFAS_Error_Mask_Upper[4:0]
This Read/Write bit-field permits the user to insert er-
rors into the upper five bits of the Framing Alignment
Signal, FAS of each outbound E3 frame. The user
may wish to do this for equipment testing purposes.
Prior to transmission, the Transmit E3 Framer block
reads in the upper five (5) bits of the FAS value, and
performs an XOR operation with it and the contents of
this register. The results of this operation are written
back into the upper five (5) bits of the FAS value, in
each outbound E3 frame. Consequently, to insure er-
rors are not injected into the FAS of the outbound E3
frames, the contents of this register must be set to all
"0’s" (the default value).
2.3.7.6 Transmit E3 FAS Error Mask Register -
1 (ITU-T G.751)
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