XRT7250 Datasheet, PDF (5/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

XRT7250 DS3/E3 FRAMER IC
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REV. 1.1.1
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ................................................................... 100
TXE3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ........................................................ 102
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) .......................................... 102
TXE3 SERVICE BITS REGISTER (ADDRESS = 0X35) ........................................................................ 103
TXE3 FAS ERROR MASK REGISTER - 0 (ADDRESS = 0X48) ............................................................ 103
TXE3 FAS ERROR MASK REGISTER - 1 (ADDRESS = 0X49) ............................................................ 104
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A) .............................................................. 104
PMON LCV EVENT COUNT REGISTER - LSB (ADDRESS = 0X51) ................................................... 105
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52) ....................... 105
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53) ........................ 105
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54) ........................................... 105
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55) ............................................ 106
PMON FEBE EVENT COUNT REGISTER - MSB (ADDRESS = 0X56) ................................................ 106
PMON FEBE EVENT COUNT REGISTER - LSB (ADDRESS = 0X57) ................................................. 106
PMON CP-BIT ERROR COUNT REGISTER - MSB (ADDRESS = 0X58) ............................................. 107
PMON CP-BIT ERROR COUNT REGISTER - LSB (ADDRESS = 0X59) .............................................. 107
PMON HOLDING REGISTER (ADDRESS = 0X6C) .............................................................................. 107
ONE-SECOND ERROR STATUS REGISTER (ADDRESS = 0X6D) ..................................................... 108
LCV - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X6E) ................................ 108
LCV - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X6F) ................................. 108
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X70) ....
109
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X71) .....
109
FRAME CP-BIT ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X72) .....
109
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X73) .....
109
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80) .................................................................. 110
LINE INTERFACE SCAN REGISTER (ADDRESS = 0X81) ................................................................... 112
2.4 THE LOSS OF CLOCK ENABLE FEATURE ......................................................................................... 112
ADDRESS = 0X01, FRAMER I/O CONTROL REGISTER ..................................................................... 113
2.5 USING THE PMON HOLDING REGISTER .......................................................................................... 113
2.6 THE INTERRUPT STRUCTURE WITHIN THE FRAMER MICROPROCESSOR INTERFACE SECTION ............. 113
BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05) .......................................................... 115
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) .......................................................... 116
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................... 118
2.7 INTERFACING THE FRAMER TO AN INTEL-TYPE MICROPROCESSOR .................................................... 118
2.8 INTERFACING THE FRAMER IC TO A MOTOROLA-TYPE MICROPROCESSOR ........................................ 121
3.0 THE LINE INTERFACE AND SCAN SECTION .............................................................................. 122
3.1 BIT-FIELDS WITHIN THE LINE INTERFACE DRIVE REGISTER .............................................................. 123
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80) .................................................................. 123
3.2 BIT-FIELDS WITHIN THE LINE INTERFACE SCAN REGISTER ............................................................... 125
LINE INTERFACE SCAN REGISTER (ADDRESS = 0X81) ................................................................... 126
XRT7250 CONFIGURATION .......................................................................................... 127
4.0 DS3 OPERATION OF THE XRT7250 ............................................................................................. 127
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................... 127
4.1 DESCRIPTION OF THE DS3 FRAMES AND ASSOCIATED OVERHEAD BITS .......................................... 127
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................... 128
4.2 THE TRANSMIT SECTION OF THE XRT7250 (DS3 MODE OPERATION) ............................................. 131
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