XRT7250 Datasheet, PDF (42/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

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DS3/E3 FRAMER IC
XRT7250
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25(C, VCC = 5.0V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP.
t_{60B “RxOH” Data Valid to rising edge of}
910
"RxOHEnable" delay
420
REV. 1.1.1
MAX.
930
UNITS
ns
CONDITIONS
DS3 Applications
440
ns E3, ITU-T G.832
Applications
Microprocessor Interface - Intel (See Figure 15)
t_{64 A8 - A0 Setup Time to ALE_AS Low}
25
32
ns E3, ITU-T G.751
Applications
4
ns
t_{65 A8 - A0 Hold Time from ALE_AS Low.}
2
ns
Intel Type Read Operations (See Figure 15 and Figure 17)
t_{66 RDS_DS*, WR_RW* Pulse Width}
60
ns
t_{67 Data Valid from RDS_DS* Low.}
6
11
ns
t_{68 Data Bus Floating from RDS_DS* High}
7
12
ns
t_{69 ALE to RD Time}
4
ns
t_{701 RD Time to "NOT READY" (e.g., RDY_DTCK tog-}
gling "Low")
6
ns
t_{70 RD to READY Time (e.g., RDY_DTCK toggling}
15
"high")
70
ns
t_{76 Minimum Time between Read Burst Access (e.g.,}
30
ns
the rising edge of RD to falling edge of RD)
Intel Type Write Operations (Figure 16 and Figure 18)
t_{71 Data Setup Time to WR_RW* High}
4
ns
t_{72 Data Hold Time from WR_RW* High}
2
ns
t_{73 High Time between Reads and/or Writes}
30
ns
t_{74 ALE to WR Time}
4
ns
t_{77 Min Time between Write Burst Access (e.g., the ris-} 30
ns
ing edge of WR to the falling edge of WR)
t_{770 CS Assertion to falling edge of WR_RW}
20
ns
Microprocessor Interface - Motorola Read Operations (See Figure 19 and Figure 21)
t_{78 A8 - A0 Setup Time to falling edge of ALE_AS}
5
ns
t_{79 Rising edge of RD_DS to rising edge of}
0
ns
“RDY_DTCK” delay
t_{80 Rising edge of “RDY_DTCK” to tri-state of D[7:0]}
0
ns
Microprocessor Interface - Motorola Read & Write Operations (See Figure 19, Figure 20, Figure 21 and Figure 22)
23