XRT7250 Datasheet, PDF (211/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

XRT7250 DS3/E3 FRAMER IC
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REV. 1.1.1
Whenever the Receive DS3 Framer block declares
OOF after being in the In-Frame State the following
will happen.
• The Receive DS3 Framer will assert the RxOOF
output pin (e.g., toggles it "High").
• Bit 4 (RxOOF) within the Rx DS3 Configuration and
Status Register will be set to "1" as depicted below.
Rx DS3 Configuration and Status Register, (Address
= 0x10)
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
BIT 7
RxAIS
BIT 6
RxLOS
BIT 5
RxIdle
BIT 4
RxOOF
R/O
R/O
R/O
R/O
X
X
X
X
• The Receive DS3 Framer block will also issue a
Change in OOF Status interrupt request, anytime
there is a change in the OOF status.
4.3.2.3 Forcing a Reframe via Software Com-
mand
The Framer IC permits the user to force a reframe
procedure of the Receive DS3 Framer block via soft-
ware command. If the user writes a "1" into Bit 0 the
I/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 3
BIT2
BIT 1
BIT 0
Int LOS
Disable
R/W
X
Framing on
Parity
R/W
X
F-Sync Algo M-Sync Algo
R/W
R/W
X
X
I/O Control Register, as depicted below, then the Re-
ceive DS3 Framer will be forced into the Frame Acqui-
sition Mode, (or more specifically, in the F-Bit Search
State per Figure 81). Afterwards, the Receive DS3
Framer block will begin its search for valid F-Bits. The
Framer IC will also respond to this command by as-
serting the RxOOF output pin, and generating a
Change in OOF Status interrupt.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Disable
TxLOC
R/W
1
LOC
RO
0
Disable
RxLOC
R/W
1
AMI/ZeroSup*
R/W
0
Unipolar/
Bipolar*
R/W
0
TxLine CLK
Invert
R/W
0
RxLine CLK
Invert
R/W
0
Reframe
R/W
0
4.3.2.4 Performance Monitoring of the Receive
DS3 Framer block
The user can monitor the number of framing bit errors
(M and F bits) that have been detected by the Re-
ceive DS3 Framer block. This is accomplished by pe-
riodically reading the PMON Framing Bit Error Count
Registers (Address = 0x52 and 0x53), as depicted
below.
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X52)
BIT 7
RO
1
BIT 6
RO
0
BIT 5
RO
1
BIT 4
BIT 3
F-Bit Error Count - High Byte
RO
RO
0
0
BIT2
RO
0
BIT 1
RO
0
BIT 0
RO
0
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X53)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
F-Bit Error Count - Low Byte
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
When the µP/µC reads these registers, it will read in
the number of framing bit errors that have been de-
tected since the last read of these two registers.
These registers are reset upon read.
4.3.2.5 DS3 Receive Alarms
192