XRT7250 Datasheet, PDF (162/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

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DS3/E3 FRAMER IC
XRT7250
REV. 1.1.1
edge of the TxNibClk output clock signal. The
XRT7250 will indicate that it is processing the last
nibble, within a given DS3 frame, by pulsing its TxNib-
Frame output pin "High" for one TxNibClk clock peri-
od. When the Terminal Equipment detects a pulse at
its Tx_Start_of_Frame input pin, it is expected to
transmit the first nibble, of the very next outbound
DS3 frame to the XRT7250 via the
DS3_Data_Out[3:0] (or TxNib[3:0] pins).
Finally, for the Nibble-Parallel Mode operation, the
XRT7250 will continuously pull the TxOHInd output
pin "Low".
The behavior of the signals between the XRT7250
and the Terminal Equipment for DS3 Mode 4 Opera-
tion is illustrated in Figure 51.
FIGURE 51. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT7250 AND THE TERMINAL EQUIP-
MENT (MODE 4 OPERATION)
Terminal Equipment Signals
RxOutClk
DS3_Nib_Clock_In
DS3_Data_Out[3:0]
Tx_Start_of_Frame
Nibble [1175]
Nibble [0]
XRT7250 Transmit Payload Data I/F Signals
RxOutClk
TxNibClk
TxNib[3:0]
TxNibFrame
Nibble [1175]
Nibble [0]
DS3 Frame Number N
Note: TxNibFrame pulses high to denote
DS3 Frame Boundary.
Sampling Edge of XRT7250 Device
DS3 Frame Number N + 1
How to configure the XRT7250 into Mode 4
1. Set the NibIntf input pin "High".
2. Set the TimRefSel[1:0] bit-fields (within the
Framer Operating Mode Register) to “00" as illus-
trated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
Local Loopback
R/W
0
DS3/E3*
R/W
0
Internal LOS
Enable
R/W
1
BIT 4
RESET
R/W
0
BIT 3
Interrupt
Enable Reset
R/W
1
BIT2
Frame Format
R/W
0
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
0
0
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