XRT7250 Datasheet, PDF (100/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

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DS3/E3 FRAMER IC
XRT7250
REV. 1.1.1
field to "1" enables this interrupt. Setting this bit-field
to "0" disables this interrupt.
NOTE: For more information on this interrupt, please see
Section 4.3.6.1.8.
2.3.4.5 Receive E3 Interrupt Status Register -
1 (E3, ITU-T G.751)
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Status
OOF
Interrupt
Status
LOF
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
R/W
RO
RO
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Bit 4 - COFA (Change of Framing Alignment) In-
terrupt Status
This Reset-upon-Read bit-field will be set to "1" if the
Change of Frame Alignment interrupt has occurred
since the last read of this register.
The Receive E3 Framer will generate the Change of
Frame Alignment interrupt if it has detected a change
in frame alignment in the incoming E3 frames.
Bit 3 - OOF (Change in OOF Condition) Interrupt
Status
This Reset Upon Read bit-field is set to "1" if the Re-
ceive E3 Framer has detected a Change in the Out-
of-Frame (OOF) Condition, since the last time this
register was read. Therefore, this bit-field will be as-
serted under either of the following two conditions:
1. When the Receive E3 Framer has detected the
appropriate conditions to declare an OOF Condi-
tion.
2. When the Receive E3 Framer has transitioned
from the OOF Condition (Frame Acquisition
Mode) into the In-Frame Condition (Frame Main-
tenance mode).
NOTE: For more information of the OOF Condition, please
see Section 4.3.2.2.
Bit 2 - LOF (Change in LOF Condition) Interrupt
Status
This Reset-upon-Read bit-field will be set to "1" if a
Change in LOF Condition interrupt has occurred
since the last read of this register.
The Receive E3 Framer will generate the Change in
LOF Condition interrupt is response to either of the
following two occurrences.
1. Whenever the Receive E3 Framer transitions
from the OOF Condition state into the LOF Con-
dition state, within the E3 Framing Acquisition/
Maintenance algorithm (per Figure 114).
2. Whenever the Receive E3 Framer transitions
from the FA1, FA2 Octet Verification state to the
In-frame state, within the E3 Framing Acquisition/
Maintenance algorithm (per Figure 114).
Bit 1 - LOS (Change in LOS Condition) Interrupt
Status
This Reset Upon Read bit will be set to "1", if the Re-
ceive E3 Framer has detected a
Change in the LOS Status condition, since the last
time this register was read. This bit-field will be as-
serted under either of the following two conditions:
1. When the Receive E3 Framer detects the occur-
rence of an LOS Condition (e.g., the occurrence
of 32 consecutive spaces in the incoming E3 data
stream), and
2. When the Receive E3 Framer detects the end of
an LOS Condition (e.g., when the Receive E3
Framer detects a string 32 bits that does not con-
tain a string of four consecutive "0’s").
The local µP can determine the current state of the
LOS condition by reading bit 6 of the Rx E3 Configu-
ration and Status Register (Address = 0x11).
NOTE: For more information in the LOS of Signal (LOS)
Alarm, please see Section 4.3.2.7.
Bit 0 - AIS (Change in AIS Condition) Interrupt
Status
This Reset Upon Read bit field will be set to "1", if the
Receive E3 Framer has detected a Change in the AIS
condition, since the last time this register was read.
This bit-field will be asserted under either of the fol-
lowing two conditions:
1. When the Receive E3 Framer first detects an AIS
Condition in the incoming E3 data stream.
2. When the Receive E3 Framer has detected the
end of an AIS Condition in the incoming E3 data
stream.
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