XRT7250 Datasheet, PDF (80/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

áç
DS3/E3 FRAMER IC
XRT7250
2.3.2.8 Receive DS3 Status Register
RXDS3 STATUS REGISTER (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
Reserved
RxFERF
RO
RO
RO
RO
0
0
0
0
BIT 3
RxAIC
RO
0
REV. 1.1.1
BIT 2
RO
0
BIT 1
RxFEBE[2:0]
RO
0
BIT 0
RO
0
Bit 4 - RxFERF Indicator
This Read Only bit-field indicates whether or not the
Receive Section of the Framer device is declaring a
FERF (Far-End-Receive Failure) condition.
If this bit-field is set to "0", then the Receive Section
(of the chip) is currently not declaring an LOS condi-
tion.
If this bit-field is set to "1", then the Receive Section
(of the chip) is currently declaring an LOS condition.
NOTE: For more information on how the Receive Section of
the chip declares the FERF condition, please see Section
3.3.2.5.4.
Bit 3 - RxAIC
This Read Only bit-field reflect the value of the AIC
bit-field, within the incoming DS3 Frames, as detect-
ed by the Receive DS3 Framer. This bit-field is set to
"1" if the incoming frame is determined to be in the C-
bit Parity Format (AIC bit = 1) for at least 63 consecu-
tive frames. This bit-field is set to "0" if two (2) or
more M-frames, out of the last 15 M-frames, contain a
"0" in the AIC bit position.
Bits 2:0 - RxFEBE[2:0]
These Read-Only bit-fields reflect the FEBE value,
within the most recently received DS3 frame.
If these bit-fields are set to "111", then it indicates that
the Remote Receiving Terminal is receiving DS3
frames in an un-erred manner.
If these bit-fields are set to "011", then it indicates that
the Remote Receiving Terminal has detected Fram-
ing or Parity bit errors in the DS3 frames that it is re-
ceiving.
NOTE: For more information on FEBE (Far-End-Block
Error) please see Section 3.3.2.5.5.
2.3.2.9 Receive DS3 Interrupt Enable Register
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP Bit Error
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
Idle Interrupt
Enable
FERF
Interrupt
Enable
AIC
Interrupt
Enable
OOF
Interrupt
Enable
P-Bit Error
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 - CP Bit Error Interrupt Enable
This Read/Write bit-field is used to enable or disable
the CP-Bit Error Interrupt. Setting this bit-field to “1’
enables this interrupt. Setting this bit-field to “0” dis-
ables this interrupt.
NOTE: For more information on the CP-Bit Error Checking/
Detection, please see Section 3.3.2.6.2.
Bit 6 - LOS Interrupt Enable
This Read/Write bit-field is used to enable or disable
the Change in LOS condition interrupt. Setting this
bit-field to "1" enables this interrupt. Setting this bit-
field to "0" disables this interrupt.
NOTE: For more information on the LOS Condition, please
see Sections 3.3.2.5.1.
Bit 5 - AIS Interrupt Enable
This Read/Write bit-field is used to enable or disable
the Change in AIS condition interrupt. Setting this bit-
field to "1" enables this interrupt. Setting this bit-field
to "0" disables this interrupt.
NOTE: For more information on the AIS Condition, please
see Sections 3.3.2.5.2.
Bit 4 - Idle Interrupt Enable
This Read/Write bit-field is used to enable or disable
the Change in Idle condition interrupt. Setting this bit-
field to "1" enables this interrupt. Setting this bit-field
to "0" disables this interrupt.
NOTE: For more information on the Idle Condition, please
see Section 3.3.2.5.3.
61