XRT7250 Datasheet, PDF (308/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

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XRT7250
DS3/E3 FRAMER IC
REV. 1.1.1
FIGURE 134. WAVEFORM/TIMING RELATIONSHIP BETWEEN RXLINECLK, RXPOS AND RXNEG - WHEN RXPOS AND
RXNEG ARE TO BE SAMPLED ON THE FALLING EDGE OF RXLINECLK
RxLineClk
t40
t41
RxPOS
RxNEG
5.3.2 The Receive E3 Framer Block
The Receive E3 Framer block accepts decoded E3
data from the Receive E3 LIU Interface block, and
routes data to the following destinations.
• The Receive Payload Data Output Interface Block
• The Receive Overhead Data Output Interface
Block.
• The Receive E3 HDLC Controller Block
Figure 135 presents a simple illustration of the Re-
ceive E3 Framer block along with the associated
paths to the other functional blocks within the Framer
chip.
FIGURE 135. A SIMPLE ILLUSTRATION OF THE RECEIVE E3 FRAMER BLOCK AND THE ASSOCIATED PATHS TO THE
OTHER FUNCTIONAL BLOCKS
To Receive E3 HDLC
Buffer
Receive Overhead Data
Output Interface
RReecceeiviveeEE33FFrraammeerr
BBlolocckk
From Receive E3
LIU Interface Block
Receive Payload Data
Output Interface
Once the HDB3 (or AMI) encoded data has been de-
coded into a binary data-stream, the Receive E3
Framer block will use portions of this data-stream in
order to synchronize itself to the remote terminal
equipment. At any given time, the Receive E3 Fram-
er block will be operating in one of two modes.
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