XRT7250 Datasheet, PDF (366/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

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XRT7250
DS3/E3 FRAMER IC
REV. 1.1.1
the TxNibClk output clock signal. The XRT7250 will
indicate that it is processing the last nibble, within a
given E3 frame, by pulsing its TxNibFrame output pin
"High" for one TxNibClk clock period. When the Ter-
minal Equipment detects a pulse at its
Tx_Start_of_Frame input pin, it is expected to trans-
mit the first nibble, of the very next Outbound E3
frame to the XRT7250 via the E3_Data_Out[3:0] (or
TxNib[3:0] pins).
Finally, for the Nibble-Parallel Mode operation, the
XRT7250 will pulse the TxOHInd output pin “High” for
a total of 14 nibble periods (e.g., for the 7 overhead
bytes, within each of the E3, ITU-T G.832 frames). At
the beginning of an E3 frame, the XRT7250 will pulse
the TxOHInd output pin “High” for 4 nibble periods.
These four nibbles represent the “FA1” and “FA2”
bytes within each E3 frame. Throughout the remain-
der of the E3 framing period, the XRT7250 will pulse
the TxOHInd output pin 5 times. The width (or dura-
tion) of each of these pulses will be two nibbles.
Clearly, each of these 5 pulses corresponds to the
five remaining overhead bytes, within the E3, ITU-T
G.832 framing structure.
The behavior of the signals between the XRT7250
and the Terminal Equipment for E3 Mode 4 Operation
is illustrated in Figure 164.
FIGURE 164. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT7250 AND THE TERMINAL EQUIP-
MENT (MODE 4 OPERATION)
Terminal Equipment Signals
RxOutClk
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
Payload Nibble [1059]
Overhead Nibble [0]
XRT7250 Transmit Payload Data I/F Signals
RxOutClk
TxNibClk
TxNib[3:0]
TxNibFrame
Nibble [1059]
Overhead Nibble [0]
TxOH_Ind
Note: TxNibFrame pulses high to denote
E3 Frame Boundary.
E3 Frame Number N
E3 Frame Number N + 1
TxOH_Ind pulses high for 4 Nibble periods
How to configure the XRT7250 into Mode 4
1. Set the NibIntf input pin "High".
2. Set the TimRefSel[1:0] bit-fields (within the
Framer Operating Mode Register) to "00" as illus-
trated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
Local Loopback DS3/E3*
BIT 5
Internal LOS
Enable
BIT 4
RESET
BIT 3
BIT2
Interrupt Frame Format
Enable Reset
BIT 1
BIT 0
TimRefSel[1:0]
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