XRT7250 Datasheet, PDF (207/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

XRT7250 DS3/E3 FRAMER IC
REV. 1.1.1
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FIGURE 79. WAVEFORM/TIMING RELATIONSHIP BETWEEN RXLINECLK, RXPOS AND RXNEG - WHEN RXPOS AND
RXNEG ARE TO BE SAMPLED ON THE FALLING EDGE OF RXLINECLK
RxLineClk
t40
t41
RxPOS
RxNEG
4.3.2 The Receive DS3 Framer Block
The Receive DS3 Framer block accepts decoded
DS3 data from the Receive DS3 LIU Interface block,
and routes data to the following destinations.
• The Receive Payload Data Output Interface Block
• The Receive Overhead Data Output Interface
Block.
• The Receive DS3 HDLC Controller Block
Figure 80 presents a simple illustration of the Receive
DS3 Framer block along with the associated paths to
the other functional blocks within the Framer chip.
FIGURE 80. A SIMPLE ILLUSTRATION OF THE RECEIVE DS3 FRAMER BLOCK AND THE ASSOCIATED PATHS TO THE
OTHER FUNCTIONAL BLOCKS
To Receive DS3 HDLC
Buffer
Receive Overhead Data
Output Interface
Receive Payload Data
Output Interface
RReecceeiviveeDDSS33FFrraammeerr
BBlolocckk
From Receive DS3
LIU Interface Block
188