XRT7250 Datasheet, PDF (248/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

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DS3/E3 FRAMER IC
XRT7250
REV. 1.1.1
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
CP-Bit Error
Interrupt
Status
RUR
0
BIT 6
LOS
Interrupt
Status
RUR
0
BIT 5
AIS
Interrupt
Status
RUR
0
BIT 4
Idle Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
AIC
Interrupt
Status
RUR
1
BIT 1
OOF
Interrupt
Status
RUR
0
BIT 0
P-Bit Error
Interrupt
Status
RUR
0
Whenever the Terminal Equipment encounters this in-
terrupt, it should do the following.
• It should continue to check the state of the AIC bit,
in order to see if this change is constant.
• If this change is constant, then the user should con-
figure the XRT7250 Framer IC to operate in the
M13 framing format, if the AIC bit-field is “0”.
• Conversely, if the AIC bit-field is “1”, then the user
should configure the XRT7250 Framer IC to oper-
ate in the C-bit Parity framing format.
4.3.6.2.7 The Detection of P-Bit Error Interrupt
If the Detection of P-Bit Error Interrupt is enabled,
then the XRT7250 Framer IC will generate an inter-
rupt, anytime the Receive DS3 Framer block has de-
tected a P-bit error, within the incoming DS3 data
stream.
Enabling and Disabling the Detection of P-Bit Er-
ror Interrupt:
The user can enable or disable the Detection of P-Bit
Error Interrupt, by writing the appropriate value into
Bit 0 (P-Bit Error Interrupt Enable) within the RxDS3
Interrupt Enable Register, as illustrated below.
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
CP Bit Error
Interrupt
Enable
R/W
0
BIT 6
LOS
Interrupt
Enable
R/W
0
BIT 5
AIS
Interrupt
Enable
R/W
0
BIT 4
Idle Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
0
BIT 2
AIC
Interrupt
Enable
R/W
0
BIT 1
OOF
Interrupt
Enable
R/W
0
BIT 0
P-Bit Error
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Detection of P-Bit Error Interrupt
Whenever the XRT7250 Framer IC detects this inter-
rupt, it will do all of the following.
• It will assert the Interrupt Request output pin (INT)
by driving it "High".
• It will set Bit 0 (P-Bit Error Interrupt Status) within
the Rx DS3 Interrupt Status Register, to “1”, as indi-
cated below.
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
CP-Bit Error
Interrupt
Status
RUR
0
BIT 6
LOS
Interrupt
Status
RUR
0
BIT 5
AIS
Interrupt
Status
RUR
0
BIT 4
Idle Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
AIC
Interrupt
Status
RUR
0
BIT 1
OOF
Interrupt
Status
RUR
0
BIT 0
P-Bit Error
Interrupt
Status
RUR
1
Whenever the Terminal Equipment encounters the
Detection of P-bit Error Interrupt, It should read the
contents of PMON Parity Error Count Register (locat-
ed at 0x54 and 0x55), in order to determine the num-
ber of P-bit errors recently received.
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