XRT7250 Datasheet, PDF (40/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

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DS3/E3 FRAMER IC
XRT7250
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25(C, VCC = 5.0V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP.
t_{27 TxInClk clock (falling) edge to “TxOHIns” hold-time} 100
50
REV. 1.1.1
MAX.
UNITS
ns
CONDITIONS
DS3 Applications
ns E3, ITU-T G.832
Applications
12
t_{28 “TXOHIns” to “TxInClk” (falling edge) set-up Time}
920
140
ns E3, ITU-T G.751
Applications
ns DS3 Applications
ns E3, ITU-T G.832
Applications
20
t_{29 TxInClk clock (falling) edge to “TxOHIns” hold-time} 100
50
ns E3, ITU-T G.751
Applications
ns DS3 Applications
ns E3, ITU-T G.832
Applications
12
t_{29A “TxOHEnable” to “TxOHIns/TxOH” Delay}
1
Transmit LIU Interface Timing (see Figure 7 and Figure 8)
t_{30 Rising edge of "TxLineClk" to rising edge of}
1
2.0
"TxPOS" or "TxNEG" output signal.
(Framer is configured to output data on "TxPOS"
and "TxNEG" on rising edge of "TxLineClk"
t_{31 Falling edge of "TxLineClk" to rising edge of}
1
4
"TxPOS" or "TxNEG"
(Framer is configured to output data via "TxPOS"
and "TxNEG" on falling edge of "TxLineClk")
f_{TxLineClk Period of TxLineClk clock signal}
44.736
f_{TxLineClk Period of TxLineClk clock signal}
34.368
t_{32 Period of TxLineClk}
22.36
t32 _{Period of TxLineClk}
29.10
Receive LIU Interface Timing (see Figure 9 and Figure 10)
t_{38 "RxPOS" or "RxNEG" set-up time to rising edge of}
3
"RxLineClk".
(Framer is configured to sample data on "RxPOS"
and "RxNEG" input pins, on the rising edge of "RxLi-
neClk")
t_{39 "RxPOS" or "RxNEG" hold time, from rising edge of}
5
"RxLineClk"
(Framer is configured to sample data on "RxPOS"
and "RxNEG" input pins, on the rising edge of "RxLi-
neClk")
ns E3, ITU-T G.751
Applications
ns
ns
ns
MHz
Mhz
ns
ns
DS3 Applications
E3 Applications
DS3 Applications
E3 Applications
ns
ns
21