XRT7250 Datasheet, PDF (124/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

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DS3/E3 FRAMER IC
XRT7250
REV. 1.1.1
PMON LCV EVENT COUNT REGISTER - LSB (ADDRESS = 0X51)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
LCV Count - Low Byte
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
This Reset-upon-Read register, along with the PMON
LCV Event Count Register - LSB (Address = 0x50)
contains a 16-bit representation of the number of Line
Code Violations that have been detected by the Re-
ceive E3 Framer, since the last read of these regis-
ters. This register contains the LSB (or Lower-Byte)
value of this 16 bit expression.
2.3.8.3 PMON Framing Bit/Byte Error Count
Register - MSB
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Framing Bit/Byte Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON
Framing Bit/Byte Error Count Register - LSB (Ad-
dress = 0x53) contains a 16-bit representation of the
number of Framing Bit or Byte Errors that have been
detected by the Receive DS3/E3 Framer, since the
last read of these registers. This register contains the
MSB (or Upper-Byte) value of this 16 bit expression.
2.3.8.4 PMON Framing Bit/Byte Error Count
Register - LSB
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Framing Bit/Byte Error Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON
Framing Bit/Byte Error Count Register - MSB (Ad-
dress = 0x52) contains a 16-bit representation of the
number of Framing Bit or Byte Errors that have been
detected by the Receive DS3/E3 Framer, since the
last read of these registers. This register contains the
LSB (or Lower-Byte) value of this 16 bit expression.
2.3.8.5 PMON Parity Error Count Register -
MSB
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Parity Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON contains a 16-bit representation of the number of P-
Parity Error Count Register - LSB (Address = 0x55) bit Errors (for DS3 applications), BIP-4 Errors (for E3/
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