XRT7250 Datasheet, PDF (132/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

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DS3/E3 FRAMER IC
XRT7250
checks for signal transitions at the TxInClk and RxLi-
neClk input pins. If a Loss of Clock Signal event oc-
cur such that no transitions are occurring on these
pins, then the LOC circuitry will automatically assert
the RDY_DTCK signal in order to complete (or termi-
REV. 1.1.1
nate) the current Read or Write cycle with the Framer
Microprocessor Interface section.
The user may enable or disable this LOC Protection
feature by writing to Bit 7 (LOC Enable) within the
Framer I/O Register, as depicted below.
ADDRESS = 0X01, FRAMER I/O CONTROL REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
LOC Enable Test PMON
Interrupt
Enable
Reset
AMI/B3ZS*
Unipolar/
Bipolar*
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
BIT 2
TxLine
Clk Inv
R/W
0
BIT 1
RxLine
Clk Inv
R/W
0
BIT 0
Reframe
R/W
0
Writing a "1" to this bit-field enables this LOC Protec-
tion feature. Writing a "0" to this bit-field disables this
feature.
NOTE: The Ring Oscillator can be a source of noise, within
the Framer chip. Hence, there may be situations where the
user will wish to disable the LOC Protection feature.
2.5 USING THE PMON HOLDING REGISTER
The Microprocessor Interface section consists of an
8-bit bi-directional data bus. As a consequence, the
local µP will be able to read from and write to the
Framer on-chip registers, 8 bit per (read or write) cy-
cle. Since most of the Framer on-chip registers con-
tain 8-bits, communicating with the local µP, over an
8-bit data bus, is not much of an inconvenience.
However, all of the PMON registers, within the Framer
IC, contain 16 bits. Consequently, any reads of the
PMON registers, will require two read cycles.
The XRT7250 Framer IC includes a feature that will
make reading a PMON register a slightly less compli-
cated task. The Framer chip address space contains
a register known as the PMON Holding register,
which is located at 0x6C. Whenever the local µP
reads in an 8-bit value of a given PMON registers
(e.g., either the upper-byte or the lower byte value of
the PMON register), the other 8-bit value of that
PMON register will automatically be accessible by
reading the PMON Holding register.
Hence, anytime the local µP is trying to read in the
contents of a PMON register, the first read access
must be made directly to one of the 8-bit values of the
PMON registers (e.g., for example: the PMON LCV
Event Count Register - MSB, Address = 0x50). How-
ever, the second read can always be made to a con-
stant location in system memory, the PMON Holding
Register.
2.6 THE INTERRUPT STRUCTURE WITHIN THE FRAMER
MICROPROCESSOR INTERFACE SECTION
The XRT7250 Framer device is equipped with a so-
phisticated Interrupt Servicing Structure. This Inter-
rupt Structure includes an Interrupt Request output,
INT, numerous Interrupt Enable Registers and numer-
ous Interrupt Status Registers. The Interrupt Servic-
ing Structure, within the Framer contains two levels of
hierarchy. The top level is at the functional block level
(e.g., the Receive Section, the Transmit Section, etc.).
The lower hierarchical level is at the individual inter-
rupt or source level. Each hierarchical level consists
of a complete set of Interrupt Status Registers/bits
and Interrupt Enable Registers/bits, as will be dis-
cussed below.
Both of the functional sections, within the Framer, are
capable of generating Interrupt Requests to the local
µP/µC. The Framer device Interrupt Structure has
been carefully designed to allow the user to quickly
determine the exact source of the interrupt (with mini-
mal latency) which will aid the local µP/µC in deter-
mining which interrupt service routine to call up in or-
der to respond to or eliminate the condition(s) caus-
ing the interrupt.
Table 5 lists all of the possible conditions that can
generate interrupts, with each functional section of
the Framer IC.
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