XRT7250 Datasheet, PDF (206/463 Pages) Exar Corporation – DS3/E3 FRAMER IC

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DS3/E3 FRAMER IC
XRT7250
REV. 1.1.1
II/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
BIT 6
BIT 5
BIT 4
Disable
TxLOC
R/W
1
LOC
RO
0
Disable
RxLOC
R/W
1
AMI/ZeroSup*
R/W
0
Table 36 depicts the relationship between the value of
this bit-field to the sampling clock edge of RxLineClk.
BIT 3
Unipolar/
Bipolar*
R/W
0
BIT2
TxLine CLK
Invert
R/W
0
BIT 1
RxLine CLK
Invert
R/W
0
BIT 0
Reframe
R/W
0
TABLE 36: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER,
AND THE SAMPLING EDGE OF THE RXLINECLK SIGNAL
RXCLKINV
(BIT 1)
RESULT
0
Rising Edge:
RxPOS and RxNEG are sampled at the rising edge of RxLineClk. See Figure 78 for timing relationship
between RxLineClk, RxPOS, and RxNEG.
1
Falling Edge:
RxPOS and RxNEG are sampled at the falling edge of RxLineClk. See Figure 79 for timing relationship
between RxLineClk, RxPOS, and RxNEG.
Figure 78 and Figure 79 present the Waveform and
Timing Relationships between RxLineClk, RxPOS
and RxNEG for each of these configurations.
FIGURE 78. WAVEFORM/TIMING RELATIONSHIP BETWEEN RXLINECLK, RXPOS AND RXNEG - WHEN RXPOS AND
RXNEG ARE TO BE SAMPLED ON THE RISING EDGE OF RXLINECLK
t42
RxLineClk
t38
t39
RxPOS
RxNEG
187