AMD-766 Datasheet, PDF (93/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
9 Test
The IC includes five NAND trees for continuity testing. It is also possible to place all the IO pins into the high-
impedance state. These modes are entered by asserting the following pins:
Mode
Equation to enable mode
High Impedance ^{~TEST# & PWRGD & ~PGNT# & ~SERR#}
NAND Tree ^{~TEST# & PWRGD & ~PGNT# & SERR#}
9.1 High Impedance Mode
When in high impedance mode, all the signals on the IC are placed into the high impedance state.
9.2 NAND Tree Mode
There are five NAND trees in the IC. The following diagram shows how these are connected, using example signals
from NAND tree 1.
VDD
SA1
SA0
… ^GPIO17
LDRQ1#
BCLK signal
…
1
To BCLK pin
0
NAND Tree Mode
When in NAND tree mode, the five NAND tree output signals are enabled and the remaining signals are in high-
impedance mode. The following pins are not part of the NAND tree: RTCX_IN, RTCX_OUT, PWRGD, PCLK,
TEST#, PGNT#, and SERR#.
The following tables provide the signal order and output signal for each NAND tree.
NAND tree 1: output signal BCLK.
1 SA1
2 SA0
3 GPIO17
4 SD4
5 GPIO19
6 LA23
7 SD3
8 GPIO18
9 LA22
10 EKIRQ12
11 SD2
12 IRQ10
13 LA21
14 SD1
15 SD0
16 IRQ11
17 LA20
18 IOCHRDY
19 GPIO25
20 IRQ12
21 LA19
22 GPIO21
23 SA16
24 IRQ15
25 LA18
26 GPIO20
27 IOW#
28 IRQ14
29 LA17
30 IOR#
31 CPUSLEEP# 41 LAD1
32 KA20G
42 GPIO2
33 MEMR# 43 PRDY
34 MEMW# 44 LAD2
35 KBRC#
45 GPIO29
36 GPIO9
46 EKIRQ1
37 LAD0
47 SA13
38 STRAPL2 48 LAD3
39 SA14
49 GPIO28
40 SA15
50 GPIO23
51 SA12
52 LFRAME#
53 GPIO31
54 SA10
55 SA11
56 LDRQ0#
57 GPIO30
58 SA9
59 LDRQ1#
93