AMD-766 Datasheet, PDF (20/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
• PCI and SCI interrupts are designed to be level triggered.
• PNP interrupts may be level or edge triggered. The inverter available in the GPIO register must be employed to
preserve the polarity from the external signal to the PIC; if this inverter is not selected, then there is an inversion
from the external signal to the PIC.
• IRQ14 and IRQ15 change from external interrupts to native mode interrupts driven by the IDE drives if
C1A08[8 and 10] are set respectively. As native mode interrupts, they are still required to be active high
(externally); they are combined with PIRQA# logic to become level-triggered, active low signals into the PIC.
• The keyboard and mouse interrupts, EKIRQ1 and EKIRQ12, are ANDed with the serial IRQ versions to go to
the USB keyboard emulation logic. The outputs of this logic enter the routing equations.
• In order for the USB keyboard and mouse emulation interrupts to function properly, either EKIRQ1 and
EKIRQ12 must be strapped low or the keyboard controller must keep the serial IRQ slots for IRQ1 and IRQ12
low.
4.3.4.2 IOAPIC
The IOAPIC supports 24 interrupt signals which come from the interrupt routing logic, the PCI interrupts, GPIOs,
the SCI interrupt, the SMI interrupt, and internal signals. Each interrupt corresponds with a redirection register that
specifies the IOAPIC behavior for the interrupt. When the IOAPIC is enabled, it transmits interrupt messages to the
processor through the 3-signal interrupt message bus (IMB), PICCLK and PICD[1:0]#.
4.3.4.2.1 WSC#
The WSC# signal is used to allow upstream posted writes to be visible to the host prior to interrupt message
transmission over the IMB. It connects between the IC and the system memory controller. It is enabled when the
IOAPIC is enabled (C0A4B[APICEN]).
The IC requests that the memory controller guarantee that the upstream posted write transactions in its data buffers
are visible to the host by placing a single-PCLK pulse on WSC#. When all the posted writes that were in the memory
controller when the first pulse was detected are visible to the host, then the memory controller responds with a two-
PCLK pulse back to the IC. After this is received, the IC transmits the interrupt message over the IMB.
PCLK
Request to send message
WSC#
The IC’s WSC# output enable
Memory controller WSC# OE
Interrupt Message Bus
Message is sent
The IC enables WSC# during the PCLK cycle in which it drives WSC# low and the following cycle in which WSC#
is driven high. It is expected that the memory controller enables the line for three PCLK cycles. WSC# is required to
be driven high for at least one clock before it is allowed to be driven low again.
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