AMD-766 Datasheet, PDF (37/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
C0A48: Miscellaneous Control 3 Register
Configuration space; function 0; offset: 48h Default: 00h Read-write.
7
6
5
4:3
2
1
0
MBL
Reserved Reserved SUB
IUSBEN# IDEEN# Reserved
IDEEN#. EIDE controller enable. 1=Access to all EIDE configuration and IO space registers disabled.
IUSBEN#. Internal USB controller enable. 1=Access to all USB configuration and memory space registers disabled.
SUB. Subtractive decoding select. Specifies how subtractive-decoding is handled by the IC. 00b=Subtractive-
decoding cycles claimed by the IC and routed to the ISA bus. 01b=Subtractive-decoding cycles claimed by the IC
and routed to the LPC bus. 1xb=Subtractive-decoding cycles not claimed by the IC.
MBL. Must be low. Read-write. This bit is required to be low at all times; otherwise undefined behavior will result.
C0A49: Miscellaneous Control 4 Register
Configuration space; function 0; offset: 49h Default: 08h.
Bits[2:1] may be used to lock out accesses to 8-byte blocks of CMOS RAM.
7
Reserved
6
MBL
5
Reserved
4
Reserved
3
2
1
0
ISA12MA CMLK_B8 CMLK_38 PRISCH
PRISCH. PCI access priority. Read-write. Specifies the priority order for the IC’s masters that access the PCI bus
as follows:
PRISCH Priority from highest to lowest
0
(1) ISA/LPC bus; (2) USB controller; (3) IDE controller
1
(1) ISA/LPC bus; (2) IDE controller; (3) USB controller
CMLK_38. CMOS RAM offsets 38h through 3Fh lock. Read; write 1 only. 0=Accesses to the eight bytes of
CMOS RAM (powered by the VDD_AL plane) addressed from 38h to 3Fh are read-write accessible. 1=Writes to
these bytes are ignored and read always return FFh (regardless as to which of the IO ports from 70h to 73h are used
for the access). After this bit is set high, it can only be cleared by PWRGD reset.
CMLK_B8. CMOS RAM offsets B8h through BFh lock. Read; write 1 only. 0=Accesses to the eight bytes of
CMOS RAM (powered by the VDD_AL plane) addressed from B8h to BFh are read-write accessible. 1=Writes to
these bytes are ignored and read always return FFh (regardless as to which of the IO ports from 70h to 73h are used
for the access). After this bit is set high, it can only be cleared by PWRGD reset.
ISA12MA. ISA bus selected to be 12 milliamps. Read-write. 1=The ISA bus signals source and sink up to 12
milliamps. 0=The ISA bus signals source and sink up to 24 milliamps. Signals affected by this bit are BCLK, IOR#,
IOW#, MEMR#, MEMW#, LA, SA, and SD.
MBL. Must be low. Read-write. This bit is required to be low at all times; otherwise undefined behavior will result.
C0A4A: IDE Interrupt Routing Register
Configuration space; function 0; offset: 4Ah Default: 84h Read-write.
7
6
PGNT1ST Reserved
5
Reserved
4
Reserved
3:2
MBLD
1:0
MBLD
MBLD. Must be left in their default state. Read-write. These bits are required to be left in their default state;
otherwise undefined behavior will result.
PGNT1ST. PCI grant before DMA acknowledge. 1=The IC waits until the PCI bus is granted before DMA
acknowledge is asserted to the LPC bus DMA controller for DMA/master LPC cycles. 0=DMA acknowledge is
asserted regardless of whether the PCI bus is granted to the IC. It is expected that this bit is normally low. Note:
When C0A47[PCIDTEN]=0, the state of C0A4A[PGNT1ST] is ignored and the IC always waits for the PCI bus to be
granted to the LPC DMA/master state machine before asserting the DACK# signal to DMA controller.
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