AMD-766 Datasheet, PDF (27/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
4.6.1.5.1 Transitions Between MOFF/SOFF/STD/STR and FON
In the timing diagrams, RTC refers to 32 kHz clocks cycles.
25 to 50
msec
CPURST#
PCIRST#
DCSTOP#
PWRON#
RPWRON (See note 2)
PWRGD
Resume event
VDD3
RST_SOFT
VDD_AUX
See
note 1
1 to 2
RTC
More than 50
milliseconds
2 to 3
RTC
1.5 to 2.0
milliseconds _{1.5 to 2.0}
µsec
MOFF to SOFF
SOFF/STD/STR to FON
MOFF to SOFF/STD/STR to FON
Note 1: If C3A43[G3TOS5] = 0, then the time from the end of RST_SOFT to PWRON# assertion is 1 to 2 RTC
clocks. If C3A43[G3TOS5] = 1, then the resume event must occur before PWRON# is asserted.
Note 2: RPWRON# is high during STR and low during STD and SOFF.
1 to 2 1 1
RTC RTC RTC
STPCLK#
Stop-grant cycle
SG
DCSTOP#
PCIRST#, CPURST#
PWRON#
RPWRON
PWRGD
VDD3
FON to SOFF/STD/STR
For STR
For SOFF/STD
For transitions to SOFF that are initiated by a power/sleep button override event or by PORTCF9[FULLRST], the
STPCLK# assertion and stop-grant cycles are skipped; the sequence starts with the assertion of DCSTOP#.
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