AMD-766 Datasheet, PDF (58/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
5.8 Power Management Configuration Registers (C3Axx)
These registers are in PCI configuration space, function 3. See section 5.1.2 for a description of the register naming
convention.
C3A00: System Management Vendor And Device ID
Configuration space; function 3; offset: 03-00h. Default: 7413 1022h. Read only.
31:16
15:0
DID
VID
VID. Vendor ID.
DID. System management device ID.
C3A04: System Management Status And Command Register
Configuration space; function 3; offset: 07-04h. Default: 0280 0000h. Read only.
31:16
15:0
STATUS[15:0]
COMMAND[15:0]
COMMAND[15:0]. These bits are fixed at their default values.
STATUS[15:0]. These bits are fixed at their default values.
C3A08: System Management Revision And Class Code Register
Configuration space; function 3; offset: 0B-08h. Default: 0000 0001h. Read only.
31:8
CLASSCODE
REVISION. System management silicon revision.
CLASSCODE. This register is write accessible through C3A60.
7:0
REVISION
C3A0C: System Management BIST-Header-Latency-Cache Register
Configuration space; function 3; offset: 0F-0Ch. Default: 0000 1600h.
31:24
23:16
15:8
BIST
HEADER
LATENCY
CACHE. Read only. These bits are fixed at their default values.
LATENCY. Read-write. This field controls no hardware.
HEADER. Read only. These bits are fixed at their default values.
BIST. Read only. These bits are fixed at their default values.
7:0
CACHE
C3A2C: System Management Subsystem ID and Subsystem Vendor ID Register
Configuration space; function 3; offset: 2F-2Ch. Default: 0000_0000h. Read only.
31:16
SSID
15:0
SSVENDORID
SSVENDORID and SSID. Subsystem vendor ID and subsystem ID registers. This register is write accessible
through C0A70.
C3A40: General Configuration 1 Register
Configuration space; function 3; offset: 40h. Default: 00h. Read-write.
7
6
5
4
3
2
1
0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved TH2SD
TH2SD. Throttling 2 second delay. 1=There is a 2.0 to 2.5 seconds delay after THERM# is asserted before thermal
throttling is initiated as specified by C3A50. 0=Thermal throttling is initiated immediately after THERM# is
asserted.
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