AMD-766 Datasheet, PDF (15/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
The IC also includes the following internal power plane.
VDD_AL. VDD always. This is an internal plane. It is supplied by VDD_AUX when that plane is valid or by
VDD_RTC when VDD_AUX is not valid. VDD_AL powers the real-time clock and some system management
circuitry. The pins powered by VDD_AL are: RTCX_IN, RTCX_OUT, INTRUDER#.
4 Functional Operation
The IC connects to the host memory controller through PCI bus interface as described in section 1.1.
The IC supports processor accesses to BIOS on either the ISA bus or the LPC bus as specified by the ISABIOS pin.
See section 5.1 for details about the software view of the IC. See section 5.1.2 for a description of the register naming
convention.
4.1 Overview
4.1.1 Resets
The IC generates an internal reset for the VDD_AUX power plane called RST_SOFT. RST_SOFT lasts for about 30
milliseconds after the VDD_AUX plane is greater than 2.5 volts. See section 4.6.1.5.1 for details.
PWRGD is the source of reset for some of the IC’s VDD3 logic. From this signal, RESET# and CPURST# are
derived. See section 4.6.1.5.1 for details.
It is possible to generate system resets via C0A47[SWPCIR].
Various system resets may be initiated through PORTCF9.
It is also possible to reset the processor (without clearing the cache) with an INIT interrupt through the keyboard
controller via KBRC#, the PORT92 register, or from a PCI-defined shutdown special cycle from the host.
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