AMD-766 Datasheet, PDF (87/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
PMEC: SMBus Host-As-Slave Device Address Register
IO mapped (base pointer: C3A58); offset: ED-ECh. Default: 0000h. Read only.
This register resides on the VDD_AUX power plane.
15:8
7:1
0
HSLV10DA
HSLVDA
SNPLSB
SNPLSB. Snoop command LSB. If the SMBus cycle address matches PMEF, then the cycle is assumed to be a write
word. The LSB of the command field for the cycle is placed in this bit (and the other 7 bits are placed in HSLVDA).
HSLVDA. Host-as-slave device address. When the SMBus logic determines that the current SMBus cycle is
directed to the host’s slave logic (because the address matches PMEE), then the device address transmitted to the IC
during the command phase of the cycle is latched in this register. Also, if the SMBus address matches the snoop
address in PMEF, then the cycle is assumed to be a write word and bits[7:1] of the command field for the cycle are
placed in this field.
HSLV10DA. Host-as-slave 10-bit device address LSBs. This field stores the second byte of the device address used
in 10-bit SMBus transfers to the host as a slave. If HSLVDA == 1111_0xxb, then the cycle is specified to transmit a
10-bit device address to the host-as-slave logic and the second byte of that device address is stored in this field. If
HSLVDA is any other value, then HSLV10BA is not utilized.
PMEE: SMBus Host-As-Slave Host Address Register
IO mapped (base pointer: C3A58); offset: EEh. Default: 10h. Read-write.
This register resides on the VDD_AUX power plane.
7:1
0
HSLVADDR
Reserved
HSLVADDR. Host-as-slave address. The SMBus logic compares the address generated by masters over the SMBus
to this field to determine if there is a match (also, for a match to occur, the read-write bit is required to specify a write
command). If a match occurs, then the cycle is assumed to be a write word command to the host, with the slave’s
device address transmitted during the normal command phase. The device address is captured in PMEC and the data
is capture in PMEA for the cycle. After the cycle is complete, PME0[HSLV_STS] is set.
PMEF: SMBus Snoop Address Register
IO mapped (base pointer: C3A58); offset: EFh. Default: 10h. Read-write.
This register resides on the VDD_AUX power plane.
7:1
0
SNPADDR
Reserved
SNPADDR. Snoop address. The SMBus logic compares the address generated by masters over the SMBus to this
field to determine if there is a match (regardless as to whether it is a read or a write). If there is a match, then
PME0[SNP_STS] is set after the cycle completes. If the address specified here matches PMEE, then
PME0[SNP_STS] is not set.
PM[F5:F4]: General-Purpose IO Pins GPIO[21:20] Select Registers
See PMC0 for definitions.
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