AMD-766 Datasheet, PDF (61/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
CS0MEM. PNPCS0# memory space selection. 1=PNPCS0# is asserted during accesses to the memory addresses
specified by programmable memory range monitor 1 (C3AD0 and C3AD8) and PCI accesses to this range are
claimed by the IC and routed to the ISA bus. If the PNPCS0# function is not selected by PMF6, then this bit has no
effect.
CS1IO. PNPCS1# IO space selection. 1=PNPCS1# is asserted during accesses to the IO addresses specified by
programmable IO range monitor 4 (C3A46[CS1UBM], C3AC8, and C3ACC) and PCI accesses to this range are
claimed by the IC and routed to the ISA bus. If the PNPCS1# function is not selected by PMF7, then this bit has no
effect.
CS1MEM. PNPCS1# memory space selection. 1=PNPCS1# is asserted during accesses to the memory addresses
specified by programmable memory range monitor 2 (C3AD4 and C3AD8 and PCI) and PCI accesses to this range
are claimed by the IC and routed to the ISA bus. If the PNPCS1# function is not selected by PMF7, then this bit has
no effect.
IRQ12_SEL. Pin definition select for IRQ12. This field is encoded as follows:
IRQ12_SEL Function for IRQ12 pin
00b IRQ12
01b No function (pin disabled such that interrupt request 12 to the PIC may be controlled by the mouse
interrupt, EKIRQ12, or serial IRQ12)
10b SMBALERT# input to the system management logic
11b USBOC1#, USB over current 1, to the USB controller
See section 4.3.4.1 for details about routing interrupts to the PIC.
CS0UBM. PNPCS0# upper bit mask. 1=Bits[10:8] of the IO address are masked from the PNPCS0# decode for IO
cycles. 0=Masking for PNPCS0# is only available for the eight LSBs, as specified by C3ACC[MASKIO3].
CS1UBM. PNPCS1# upper bit mask. 1=Bits[10:8] of the IO address are masked from the PNPCS1# decode for IO
cycles. 0=Masking for PNPCS1# is only available for the eight LSBs, as specified by C3ACC[MASKIO4].
C3A48: Pins Latched On The Trailing Edge Of Reset Register
Configuration space; function 3; offset: 49-48h. Default: 00??_?000_00?0_?00?b, where ?’s indicate bits that are
latched on the trailing edge of reset.
The default for some of these bits is specified by pull up or pull down resistors on pins during the trailing edge of the
specified reset (PWRGD). To latch a low from these pins, a 10K to 100K ohm resistor to ground is placed on the
signal. To latch a high from these pins, a 10K to 100K ohm resistor to the pin’s power plane is placed on the signal.
The resistors enabled by ENIDE, ENPCI, and ENISA are nominally 5K ohms. The default state of these bits are
specified by the state of the SPKR pin during reset. A pull-up resistor on SPKR causes these bits to default to high
and a pull-down resistor causes these bits to default to low.
15
Reserved
14
Reserved
13
ENIDE
12
ENPCI
11
ENISA
10
Reserved
9
Reserved
8
Reserved
7
Reserved
6
Reserved
5
MBH
4
3:2
Reserved MBL
1
Reserved
0
ISABIOS
ISABIOS. Direct BIOS accesses to the ISA bus versus the LPC bus. Read only. This reflects the state of the
ISABIOS pin. 1=ROM accesses as specified by C0A43 are routed to the ISA bus. 0=ROM accesses as specified by
C0A43 are routed to the LPC bus.
MBL. Must be low. Read-write. These bits are required to be low at all times; otherwise undefined behavior will
result. The default state of bit[3] is latched off the ROM_KBCS# pin during PWRGD reset (so a pull-down resistor
is required).
MBH. Must be high. Read-write. This bit is required to be high at all times; otherwise undefined behavior will
result. The default state of bit[3] is latched off the IOCHRDY pin during PWRGD reset (so a pull-up resistor is
required).
ENISA. Enable ISA pull-up/down resistors. Read-write. 1=The internal pull-up and pull-down resistors for the ISA
bus signals are enabled. This includes pull-ups on IOCHRDY, IOCHK#, IRQ[15,14,11:9,7:3], and SD[7:0].
0=Disable internal ISA bus resisters. The default state of this bit is latched off the SPKR pin during PWRGD reset.
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