AMD-766 Datasheet, PDF (72/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
PM20: ACPI GP Status Register
IO mapped (base pointer: C3A58); offset: 21-20h. Default: 0000h. Read; set by hardware; write 1 to clear.
Access to some of these bits is replicated in PM24 and PM28. For these bits, there is only one physical register.
These bits have the ability to generate an SCI/SMI interrupt, if they are enabled to do so in PM22.
15
14
USB_RSM_STS RI_STS
13
Reserved
12
Reserved
11
10
9
8
Reserved THERM_STS EXTSMI_STS PME_STS
7
6
5
4
3
2
1
0
TCOSCI_STS Reserved SIT_STS
Reserved
Reserved Reserved
Reserved
Reserved
SIT_STS. System inactivity timer time out status. 1=The system inactivity timer, PM98, timed out. Access to this
register is replicated in PM28.
TCOSCI_STS. TCO SCI interrupt status. 1=There was a 0 to 1 transition on PM46[INTRDR_STS] or
PM44[TCO_INT_STS].
PME_STS. PME# pin status. 1=The PME# pin was asserted. This bit resides on the VDD_AUX power plane.
Access to this register is replicated in PM28.
EXTSMI_STS. External SMI pin status. 1=The EXTSMI# pin was asserted (the active state is dependent upon the
GPIO12 input polarity). This bit resides on the VDD_AUX power plane. Access to this register is replicated in
PM28.
THERM_STS. THERM# pin status. 1=The THERM# pin was asserted. Access to this register is replicated in
PM28.
RI_STS. RI# pin status. 1=The RI# pin is asserted (the active state is dependent upon the GPIO14 input polarity).
This bit resides on the VDD_AUX power plane. Access to this register is replicated in PM28.
USB_RSM_STS. USB-defined resume event status. 1=The USB-defined resume event has occurred. This bit
resides on the VDD_AUX power plane. Access to this register is replicated in PM24.
PM22: ACPI GP Enable Register
IO mapped (base pointer: C3A58); offset: 23-22h. Default: 0000h. Read-write.
These bits work in conjunction with the corresponding bits in PM20 to generate SCI or SMI interrupts. For each of
the bits in this register: 1=Enable a corresponding status bit in PM20 to generate an SMI or SCI interrupt (based on
the state of PM04[SCI_EN]); 0=Do not enable the SMI or SCI interrupt.
15
14
USB_RSM_EN RI_EN
13
Reserved
12
Reserved
11
10
9
8
Reserved THERM_EN EXTSMI_EN PME_EN
7
6
5
4
3
2
1
0
TCOSCI_EN Reserved SIT_EN
Reserved
Reserved Reserved
Reserved
Reserved
SIT_EN. System inactivity timer time out ACPI interrupt enable.
TCOSCI_EN. TCO SCI enable. Note: When this is high, C3A44[TCO_INT_SEL] is ignored.
PME_EN. PME# pin ACPI interrupt enable.
EXTSMI_EN. External SMI pin ACPI interrupt enable.
THERM_EN. THERM# pin ACPI interrupt enable.
RI_EN. RI# pin ACPI interrupt enable.
USB_RSM_EN. USB resume event ACPI interrupt enable. Access to this bit is replicated in PM25; there is only
one physical register accessed through both PM22 and PM25.
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