AMD-766 Datasheet, PDF (31/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
5
Registers
5.1 Register Overview
The IC includes several sets of registers accessed through a variety of address spaces. IO address space refers to
register addresses that are accessed via x86 IO instructions such as IN and OUT. PCI configuration space is typically
accessed via PCI-defined IO cycles to CF8h and CFCh in the host. There is also memory space and indexed address
space in the IC.
5.1.1 Configuration Space
The address space for PCI configuration registers is broken up into busses, devices, functions, and, offsets, as defined
by the PCI specification. Configuration registers within the IC are accessed by type 0 configuration cycles. The
IDSEL pin specifies the IC as the targeted device. The function number is mapped into bits[10:8] of the
configuration address. The offset is mapped to bits[7:2] of the configuration address.
5.1.2 Register Naming And Description Conventions
Each register location has an assigned mnemonic that specifies the address space and offset. These mnemonics start
with two to four characters that identify the space followed by characters that identify the offset within the space.
Register fields within register locations are also identified with a name or bit group in brackets following the register
location mnemonic. For example, the ACPI sleep type register field, which is located at offset 04h of PMxx space,
bits10, 11, and 12, is referenced as PM04[SLP_TYP] or PM04[12:10].
PCI configuration spaces are referenced with mnemonics that takes the form of C[4:0]A[FF:0], where the first
bracket contains function number and the last bracket contains the offset.
PCI configuration spaces.
Function
Mnemonic Function
0
C0Axx PCI-ISA/LPC bridge
1
C1Axx IDE controller
2
C2Axx Not used
3
C3Axx System management registers
4
C4Axx USB controller
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