AMD-766 Datasheet, PDF (32/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
Fixed address spaces.
Port(s)
Mnemonic
00-0F
PORTxx
20-21
PORTxx
40-43
PORTxx
60, 64
PORTxx
61
PORT61
70-73
RTCxx
80-8F
PORTxx
92
PORT92
A0-A1
PORTxx
C0-DF
PORTxx
F0-F1
PORTxx
170-177, 376 PORTxxx
1F0-1F7, 376 PORTxxx
4D0-4D1
PORT4D0
CF9
PORTCF9
FEC0_0000 to
FEC0_001F
IOAxx
Type
Function
IO mapped Slave DMA controller
IO mapped Master interrupt controller
IO mapped Programmable interval timer
IO mapped USB keyboard emulation address
IO mapped AT Compatibility Register
IO mapped Real-time clock and CMOS RAM
IO mapped DMA page registers
IO mapped System control register
IO mapped Slave interrupt controller
IO mapped Master DMA controller
IO mapped Floating point error control
IO mapped Secondary IDE drives (not used when in native mode)
IO mapped Primary IDE drives (not used when in native mode)
IO mapped EISA-defined level-triggered interrupt control registers
IO mapped System reset register
Memory mapped IOAPIC register set
Relocatable address spaces.
Base address Mnemonic
register
Type
Size Function
(bytes)
C1A10
None
IO mapped
8 Pointer to primary port IDE command space
C1A14
None
IO mapped
4 Pointer to primary port IDE control space
C1A18
None
IO mapped
8 Pointer to secondary port IDE command space
C1A1C
None
IO mapped
4 Pointer to secondary port IDE control space
C1A20
IBMx
IO mapped
16 IDE controller bus master control registers
C3A58
PMxx
IO mapped 256 System management IO register space
C4A10
USBxxx Memory mapped 4K USB IO register space
Note: C1A10, C1A14, C1A18, and C1A20 are only used when the IDE controller is in native mode as specified by
C1A08.
The following are register behaviors found in the register descriptions.
Type
Description
Read or read only
Write
Set by hardware
Write 1 to clear
Write 1 only
Write once
Capable of being read by software. Read only implies that the register cannot be written to by
software.
Capable of being written by software.
Register bit is set high hardware.
Software must write a 1 to the bit in order to clear it. Writing a 0 to these bits has no effect.
Software may set the bit high by writing a 1 to it. However subsequent writes of 0 have no
effect. RESET# must be asserted in order to clear the bit.
After RESET#, these registers may be written to once. After they are written, they become
read only until the next RESET# assertion.
32