AMD-766 Datasheet, PDF (83/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
GPIO Control Signal Name Default
MODE Alternate Functions Input Notes
name
register
Path
GPIO[0] PMC0 SMBUSC 08h (SMBUSC)
1xb SMBUSC
Direct 2
GPIO[1] PMC1 SMBUSD 08h (SMBUSD)
1xb SMBUSD
Direct 2
GPIO[2] PMC2 GPIO2
00h (GPIO input)
1
GPIO[3] PMC3 SLPBTN# 0Ch (SLPBTN#)
1xb SLPBTN#
GPIO 1, 2
GPIO[4] PMC4 SUSPEND# 08h (SUSPEND#)
1xb SUSPEND#
NA
GPIO[5] PMC5 CPUSLEEP# 05h (GPIO output, high) 1xb CPUSLEEP#
NA
GPIO[6] PMC6 CPUSTOP# 05h (GPIO output, high) 1xb CPUSTOP#
NA
GPIO[7] PMC7 PCISTOP# 05h (GPIO output, high) 1xb PCISTOP#
NA
GPIO[8] PMC8 CACHE_ZZ 04h (GPIO output, low) 1xb CACHE_ZZ
NA
GPIO[9] PMC9 GPIO9
05h (GPIO output, high)
GPIO[10] PMCA FLAGWR 04h (GPIO output, low) 1xb FLAGWR
NA
GPIO[11] PMCB FLAGRD# 05h (GPIO output, high) 1xb FLAGRD#
NA
GPIO[12] PMCC EXTSMI# 0Ch (EXTSMI#)
1xb EXTSMI#
GPIO 2
GPIO[13] PMCD PRDY
0Ch (No function)
10b PRDY
Direct
11b No function (input)
NA
GPIO[14] PMCE RI#
08h (RI#)
1xb RI#
GPIO 2
GPIO[15] PMCF C32KHZ 04h (GPIO output, low) 1xb C32KHZ
NA
GPIO[16] PMD0 INTIRQ8# 05h (GPIO output, high) 10b INTIRQ8#
NA
11b SQWAVE
NA
GPIO[17] PMD1 GPIO17
00h (GPIO input)
GPIO[18] PMD2 GPIO18
00h (GPIO input)
1xb PNPIRQ0
GPIO
GPIO[19] PMD3 GPIO19
00h (GPIO input)
1xb PNPIRQ1
GPIO
GPIO[20] PMF4 GPIO20
00h (GPIO input)
1xb PNPIRQ2
GPIO
GPIO[21] PMF5 GPIO21
08h (BMREQ#)
1xb BMREQ#
Direct 3
GPIO[22] PMF6 GPIO22
05h (GPIO output, high) 1xb PNPCS0#
NA
GPIO[23] PMF7 GPIO23
05h (GPIO output, high) 1xb PNPCS1#
NA
GPIO[24] PMF8 GPIO24
05h (GPIO output, high)
GPIO[25] PMF9 GPIO25
04h (GPIO output, low)
GPIO[26] PMFA GPIO26
04h (GPIO output, low)
GPIO[27] PMFB GPIO27
04h (GPIO output, low)
GPIO[28] PMFC GPIO28
00h (GPIO input)
GPIO[29] PMFD GPIO29
00h (GPIO input)
GPIO[30] PMFE GPIO30
00h (GPIO input)
GPIO[31] PMFF GPIO31
00h (GPIO input)
Note 1: The output of the input path for GPIO[17, 16, 3, 2] is also routed to the IOAPIC to drive the interrupt
request inputs to some of the redirection register entries (see section 4.3.4.2.2). These signals, to the
IOAPIC, are never disabled, even if the alternate function is selected.
Note 2: PMC0, PMC1, PMC3, PMCC, and PMCE all reside on the VDD_AUX power plane.
Note 3: If PMF5 does not select the BMREQ# function, then IRQ[11:9, 7:3] are selected to be the REQ[7:0]#
function.
PMD4: GPIO Pin Interrupt Status Register
IO mapped (base pointer: C3A58); offset: D7-D4h. Default: 0000_0000h. Read; set by hardware; write 1 to clear.
Each of these status bits is driven by the output of the input circuit associated with the GPIO pins. Bit[0] corresponds
to GPIO 0; bit[1] corresponds to GPIO1, and so forth. The latch associated with each GPIO input circuit is cleared
when the corresponding bit in this register is written with a 1; writing a 0 has no effect.
31:0
GPIO IRQ status bits
83