AMD-766 Datasheet, PDF (25/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
4.6.1.3 System Inactivity Timer
The system inactivity timer is an 8-bit down counter that is controlled through PM98. Any of the hardware traps,
IRQ lines, or PCI bus master activity may be enabled to reload the system inactivity timer through PMB0 and PMB4.
If the timer decrements to zero, then, if enabled by PM22 or PM2A, an interrupt is generated.
4.6.1.4 Throttling logic
When throttling, the IC repetitively places the processor into the stop-grant state for a specified percentage of time in
order to reduce the power being consumed by the processor. STPCLK# is used to control the processor stop-grant
state with a period of 244 microseconds (based on 8 cycles of the 32.768 kHz clock) and a duty cycle as specified by
control registers C3A50 and PM10.
Two types of throttling are possible: normal and thermal. Normal throttling is controlled by software. Thermal
throttling is controlled by the THERM# pin (see also C3A40[TH2SD]). If both are enabled simultaneously, then the
duty cycle specified for thermal throttling is employed. Throttling is only possible when in the FON state. If
throttling is enabled when entering other states, then it stops; after exiting the state, throttling resumes.
4.6.1.5 System Power State Controller (SPSC)
The system power state controller (SPSC) supports the following system power states:
State
VDD3
VDD_AUX
VDD_RTC,
VDD_AL
Full on (FON)
On
On
On
C2; C3
On
On
On
Power on suspend (POS; S1)
On
On
On
Suspend to RAM (STR; S3)
Off
On
On
Soft off (SOFF; S5); suspend to disk (STD; S4) Off
On
On
Mechanical off (MOFF; G3)
Off
Off
On
Mechanical off (MOFF or ACPI G3 state). MOFF is the state when only VDD_AL is powered. This may happen at
any time, from any state, due to the loss of power to the VDD_AUX plane (e.g., a power outage, the power supply is
unplugged, or the power supply’s mechanical switch). When power is applied to VDD_AUX, then the system
transitions to either FON or SOFF.
Soft off (SOFF or ACPI G2/S5 states). In the SOFF state, the system appears to the user to be off. The IC's
VDD_AUX plane is powered, but the main supplies are not; RPWRON is low to disable power system DRAM. The
system normally uses PWRBTN# to transition from SOFF to FON. The IC also allows SMBus activity, USB resume
events, the real-time clock alarm, the EXTSMI# pin, the SLPBTN# pin, the RI# pin and the PME# pin to be enabled
to cause this transition.
Suspend to disk (STD or ACPI S4 state). The IC’s behavior in this state is equivalent to SOFF.
Suspend to RAM (STR or ACPI S3 state). In the STR state, the system’s context is stored in system memory (which
remains powered; RPWRON is high) and the main power supplies are shut off (PWRON# high). The IC’s behavior
in the STR state is similar to SOFF; the main difference is that RPWRON is asserted in STR.
Power on suspend (POS or ACPI S1 state). All power planes to the IC are valid in POS. Signal control during POS
is specified by C3A50.
Snoop-capable clock control (C2). In C2, the processor is placed into the stop-grant state. Signal control during C2
is specified by C3A50. It is expected that the processor’s cache may be snooped while in this state.
25