AMD-766 Datasheet, PDF (62/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
ENPCI. Enable PCI pull-up resistors. Read-write. 1=The internal pull-ups for PCI bus signals are enabled. This
includes pull-ups on DEVSEL#, FRAME#, IRDY#, PIRQ[A,B,C,D]#, SERR#, STOP#, TRDY#. 0=Disable internal
PCI bus resisters. The default state of this bit is latched off the SPKR pin during PWRGD reset.
ENIDE. Enable IDE pull-down resistors. Read-write. 1=The internal pull-down resistors for the IDE bus signals
are enabled. This includes pull-downs on DDRQP, DDRQS. 0=Disable internal IDE bus resisters. The default state
of this bit is latched off the SPKR pin during PWRGD reset.
C3A4A: Serial IRQ Control Register
Configuration space; function 3; offset: 4Ah. Default: 10h. Read-write.
7
6
5:2
1:0
Reserved CONTMD FRAMES
STARTCLKS
STARTCLKS. Number of clocks in start pulse. This specifies the number of clocks in the start pulse over SERIRQ
is during the start frame of a serial IRQ cycle (including the slave cycle if in quiet mode). 00b = 4 clocks; 01b = 6
clocks; 10b = 8 clocks; 11b = reserved.
FRAMES. Number if IRQ frames for a serial IRQ cycle. This specifies the number of 3-clock IRQ frames that the
IC generates during a serial IRQ cycle before issuing the stop frame. The number of frames is 17 plus the value of
this field. Thus, the number of frames varies from 17 (for a value of 0h) and to 32 (for a value of Fh).
CONTMD. Continuous mode selected versus quiet mode. 1=The serial IRQ logic is in continuous mode. In
continuous mode, the start frame is initiated by the IC immediately following each stop frame. 0=The serial IRQ
logic is in quiet mode. In quiet mode, start frames are initiated by external slave devices.
C3A4C: PRDY Timer Control Register
Configuration space; function 3; offset: 4Ch. Default: 00h. Read-write.
Each of these bits control the ability of the PRDY input signal to disable internal counters. When PRDY is active the
counters that correspond to the bits in this register that are high stop counting. If the PRDY function of the PRDY
pin is not selected by PMCD, then this register has no effect.
7
6
5
4
3
2
1
0
Reserved Reserved Reserved ACPI_DIS SIT_DIS RW
RTC_DIS PIT_DIS
PIT_DIS. Programmable interval timer disable. 1=The three timers of the internal legacy PIT stop counting when
PRDY is active.
RTC_DIS. Real time clock disable. 1=The real-time clock’s counters that are clocked off of the 32 kHz clock stop
counting while PRDY is active.
RW. Read-write. This bit is read-write accessible through software; is controls no hardware.
SIT_DIS. System inactivity timer disable. 1=The system inactivity timer specified by PM98 stops counting from
counting while PRDY is active.
ACPI_DIS. ACPI power management timer disable. 1=The ACPI timer specified by PM08 stops counting while
PRDY is active.
C3A4E: Square Wave Generation Register
Configuration space; function 3; offset: 4Eh. Default: 00h. Read-write.
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3:0
SQWAVE
SQWAVE. Square wave frequency control. When PMD0 selects square wave output function, then this field to
specifies the frequency of square wave output on the INTIRQ8# pin. The square wave output is generated by
dividing down the 32 kHz clock. This field is encoded as follows:
SQWAVE Frequency
0h
Output low
1h
256 Hz.
SQWAVE Frequency
4h
4096 Hz.
5h
2048 Hz.
SQWAVE Frequency
8h
256 Hz.
9h
128 Hz.
SQWAVE Frequency
Ch
16 Hz.
Dh
8 Hz.
2h
128 Hz.
3h
8192 Hz.
6h
1024 Hz.
Ah
64 Hz.
7h
512 Hz.
Bh
32 Hz.
Eh
4 Hz.
Fh
2 Hz.
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