AMD-766 Datasheet, PDF (22/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
4.6 System Management Logic
System management includes logic for most of the multiplexed-function pins—such as general-purpose IO (GPIO)
pins, the power management (PM) pins, system management bus (SMBus) pins, the processor interface pins, and the
plug and play (PNP) interrupt pins—as well as the logic required for ACPI-compliant power management for
desktop and mobile systems. Programmable register access to most of this logic is contained in the C3Axx
configuration space and the PMxx IO space. Here are the major functions:
• ACPI interrupt (SCI or SMI based on the state of PM04[SCI_EN] status bits and enables.
• SMI status bits and enables.
• System power state machine (SPSM).
• Resume event logic (to place the SPSM into the full-on state).
• SMBus.
• System power state control pins and general purpose pins.
• Hardware traps.
• System inactivity timer.
• Serial IRQ logic.
4.6.1 Power Management
The following table summarizes all the system management events that are detected by the system management logic
and the hardware response enable registers. The columns are STS, where the status bits are accessible, EVT, where
the grouped status bits may be read, SCI/SMI EN, where ACPI interrupts may be enabled, SMI_EN, where the SMI
interrupts may be enabled, SIT_EN, where the events may be enabled to reload the system inactivity timer, and the
resume columns which show where the registers to enable the resume events from C2, C3, POS, STD, STR, and
SOFF to FON.
22