AMD-766 Datasheet, PDF (80/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
Bit[11] PCMCIA1_TRP_STS. PCMCIA1 access trap status.
Bit[12] PCMCIA2_TRP_STS. PCMCIA2 access trap status.
Bit[13] USB_TRP_STS. USB access or activity trap status. This bit is set high by the hardware wen a USB control,
isochronous, interrupt, or bulk transfer has been attempted (at the end of the transfer across the USB bus).
Bit[14] PRM1_TRP_STS. Programmable IO range monitor 1 access trap status.
Bit[15] PRM2_TRP_STS. Programmable IO range monitor 2 access trap status.
Bit[16] PRM3_TRP_STS. Programmable IO range monitor 3 access trap status.
Bit[17] PRM4_TRP_STS. Programmable IO range monitor 4 access trap status.
Bit[18] PMM1_TRP_STS. Programmable memory range monitor 1 access trap status.
Bit[19] PMM2_TRP_STS. Programmable memory range monitor 2 access trap status.
PMAC: Hardware Trap Enable Register
IO mapped (base pointer: C3A58); offset: AF-ACh. Default: 0000_0000h. Read-write.
For each of these bits: 1=enable the corresponding bit in the hardware trap status register, PMA8, to generate SMI or
SCI interrupts (based on the state of PM04[SCI_EN]). Also, when an enabled status bit is set, PM28[TRP_EVT] is
asserted.
31:20
Reserved
19:0
Enable bits
Bit[0] DPM_TRP_EN. IDE primary master port access trap enable.
Bit[1] DPS_TRP_EN. IDE primary slave port access trap enable.
Bit[2] DSM_TRP_EN. IDE secondary master port access trap enable.
Bit[3] DSS_TRP_EN. IDE secondary slave port access trap enable.
Bit[4] FDD_TRP_EN. Floppy disk drive access trap enable.
Bit[5] LPT_TRP_EN. Parallel port (LPT) access trap enable.
Bit[6] CMA_TRP_EN. Serial port A (COM A) access trap enable.
Bit[7] CMB_TRP_EN. Serial port B (COM B) access trap enable.
Bit[8] AUD_TRP_EN. Audio functions access trap enable.
Bit[9] VID_TRP_EN. Video functions access trap enable.
Bit[10] KBM_TRP_EN. Keyboard and mouse access trap enable.
Bit[11] PCMCIA1_TRP_EN. PCMCIA1 access trap enable.
Bit[12] PCMCIA2_TRP_EN. PCMCIA2 access trap enable.
Bit[13] USB_TRP_EN. USB access or activity trap enable.
Bit[14] PRM1_TRP_EN. Programmable range monitor 1 access trap enable.
Bit[15] PRM2_TRP_EN. Programmable range monitor 2 access trap enable.
Bit[16] PRM3_TRP_EN. Programmable range monitor 3 access trap enable.
Bit[17] PRM4_TRP_EN. Programmable range monitor 4 access trap enable.
Bit[18] PMM1_TRP_EN. Programmable memory range monitor 1 access trap enable.
Bit[19] PMM2_TRP_EN. Programmable memory range monitor 2 access trap enable.
PMB0: Hardware Trap Reload Enable For System Inactivity Timer Register
IO mapped (base pointer: C3A58); offset: B3-B0h. Default: 0000_0000h. Read-write.
For bits[19:0]: 1=enables the corresponding hardware trap in PMA8 to reload the system inactivity timer.
31:22
21:0
Reserved
Reload enable bits
Bit[0] DPM_TRP_RLEN. IDE primary master port access trap causes reload of system inactivity timer.
Bit[1] DPS_TRP_RLEN. IDE primary slave port access trap causes reload of system inactivity timer.
Bit[2] DSM_TRP_RLEN. IDE secondary master port access trap causes reload of system inactivity timer.
Bit[3] DSS_TRP_RLEN. IDE secondary slave port access trap causes reload of system inactivity timer.
Bit[4] FDD_TRP_RLEN. Floppy disk drive access trap causes reload of system inactivity timer.
Bit[5] LPT_TRP_RLEN. Parallel port (LPT) access trap causes reload of system inactivity timer.
Bit[6] CMA_TRP_RLEN. Serial port A (COM A) access trap causes reload of system inactivity timer.
80