AMD-766 Datasheet, PDF (36/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
C0A43: ROM Decode Control Register
Configuration space; function 0; offset: 43h Default: 00h Read-write.
This register specifies the address space mapped to the BIOS ROM on either the ISA bus or the LPC bus (based on
the state of C3A48[ISABIOS]). The ROM_KBCS# pin is used to enable accesses to the system BIOS on the ISA bus.
LPC bus accesses are decoded by the LPC BIOS device with the LPC address map shown below.
7:0
SEGEN
SEGEN. ROM segment enables. For each of these bits: 1=Enables the specified address range as a BIOS ROM
access. 0=The specified address range is not decoded as a BIOS ROM access. These bits control the following
address ranges; the last column shows the translated LPC bus addresses if C3A48[ISABIOS]=0; the next column
shows the translated ISA bus address if C3A48[ISABIOS]=1:
SEGEN Size PCI Address Range[31:0] Address translation Address translation
bit
for ISA bus[23:0]
for LPC bus
0
32K bytes 000C_0000 - 000C_7FFFh FC_0000 - FC_7FFFh FFFC_0000 - FFFC_7FFFh
1
32K bytes 000C_8000 - 000C_FFFFh FC_8000 - FC_FFFFh FFFC_8000 - FFFC_FFFFh
2
32K bytes 000D_0000 - 000D_7FFFh FD_0000 - FD_7FFFh FFFD_0000 - FFFD_7FFFh
3
32K bytes 000D_8000 - 000D_FFFFh FD_8000 - FD_FFFFh FFFD_8000 - FFFD_FFFFh
4
32K bytes 000E_0000 - 000E_7FFFh FE_0000 - FE_7FFFh FFFE_0000 - FFFE_7FFFh
5
32K bytes 000E_8000 - 000E_FFFFh FE_8000 - FE_FFFFh FFFE_8000 - FFFE_FFFFh
6 1 megabyte FFB0_0000 - FFBF_FFFFh B0_0000 - BF_FFFFh FFB0_0000 - FFBF_FFFFh
7 4 megabytes FFC0_0000 - FFFF_FFFFh C0_0000 - FF_FFFFh FFC0_0000 - FFFF_FFFFh
Note: The following ranges are fixed BIOS address ranges:
Size PCI Address Range[31:0] Address translation Address translation
for ISA bus[23:0]
for LPC bus
64K bytes 000F_0000 - 000F_FFFFh FF_0000 - FF_FFFFh FFFF_0000 - FFFF_FFFFh
64K bytes FFFF_0000 - FFFF_FFFFh FF_0000 - FF_FFFFh FFFF_0000 - FFFF_FFFFh
Note: See C0A80 for further information about how access to BIOS spaces is controlled.
C0A46: Miscellaneous Control 1 Register
Configuration space; function 0; offset: 46h Default: 00h Read-write.
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
PMWE
PMWE. Posted memory write enable. 1=Enable the one-DWORD write buffer from PCI target memory writes to
the ISA/LPC bus. 0=The IC waits until the ISA/LPC cycle is complete before passing ready back to the PCI bus.
C0A47: Miscellaneous Control 2 Register
Configuration space; function 0; offset: 47h Default: 00h
7
CPURS
6
5
PCIDTEN Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
SWPCIR
SWPCIR. Software PCI reset. Write only. When this bit is written with a 1, a 1.5 to 2.0 millisecond reset pulse is
generated over PCIRST# and CPURST#.
PCIDTEN. PCI delayed transaction enable. Read-write. 1=PCI accesses that target the ISA/LPC bus and internal
legacy registers utilize delayed-transactions. 0=PCI accesses that target the ISA/LPC bus and internal legacy
registers are terminated after the ISA/LPC bus cycle is complete. This bit does not affect posted memory writes
(C0A46[PMWE]=1), for which always disconnect with data. Note: When PCIDTEN=0, the state of
C0A4A[PGNT1ST] is ignored and the IC always waits for the PCI bus to be granted to the LPC DMA/master state
machine before asserting the DACK# signal. It is expected that PCIDTEN is normally set high.
CPURS. CPU reset select. Read-write. 1=Processor resets are directed toward the INIT# pin. 0=Processor resets
are directed toward the CPURST# pin. This bit is required to be high.
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