AMD-766 Datasheet, PDF (29/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
4.6.2 Serial IRQ Protocol
The IC supports the serial IRQ protocol. This logic controls the SERIRQ pin and outputs IRQs to the legacy PIC and
IOAPIC blocks. This logic is synchronous with PCLK. It is specified by C3A4A. The IC does not provide support
for generating IRQ0, IRQ2, IRQ8, or IRQ13 via SERIRQ. In order to use a serial IRQ interrupt, the corresponding
external IRQ pin, EKIRQ[1, 12], IRQ[15, 14, 11:9,7:3], must be pulled high. See section 4.3.4.1 for more details.
4.6.3 SMBus Controller
The IC includes a system management bus, SMBus, controller. SMBus is a two-wire serial interface typically used to
communicate with system devices such as temperature sensors, clock chips, and batteries. The control registers for
this bus are PME0 through PMEF.
The SMBus controller includes a host controller and a host-as-slave controller.
Host controller. The host controller is used to generate cycles over the SMBus as a master. Software accomplishes
this by setting up PME2[CYCTYPE] to specify the type of SMBus cycle desired and then (or concurrently) writing a
1 to PME2[HOSTST]. This triggers an SMBus cycle with the address, command, and data fields as specified by the
registers called out in PME2[CYCTYPE].
Writes to the host controller registers PME2[3:0], PME4, PME8, and PME9 are illegal while the host is busy with a
cycle. If a write occurs to PME2 while PME0[HST_BSY] is active, then the four LSBs be ignored. Writes to PME4,
PME8, and PME9 while PME0[HST_BSY] is active are ignored (the transaction is completed, but no data is
transferred to the SMBus controller).
If an SMBus-defined time out occurs while the host is master of the SMBus, then the IC attempts to generate a
SMBus stop event to clear the cycle and PME0[TO_STS] is set.
The host controller is only available in the FON state.
Host-as-slave controller. The host-as-slave controller responds to word-write accesses to either the host address
specified by PMEE or the snoop address specified by PMEF. In either case, if the address matches, then the
subsequent data is placed in PMEC and PMEA. In the case of snoop accesses, the command information is stored in
PMEC[7:0] and the data is stored in PMEA[15:0]. In the case of addresses that match the PMEE host-as-slave
address register, then the address is stored in PMEC[7:1]—if the transaction includes a 7-bit address—or
PMEC[15:1]—if the transaction includes a 10-bit address. After the address match is detected, the IC waits for the
subsequent stop command before setting the appropriate status bits in PME0[HSLV_STS, SNP_STS]; however, if a
time out occurs during the cycle, after the address match is detected, then the appropriate bit in PME0[HSLV_STS,
SNP_STS] are set.
If one of the slave status bits, PME0[HSLV_STS, SNP_STS], is set and another access to the host slave controller is
initiated, then it is not acknowledged via the first SMBus acknowledge cycle until the status bit is cleared.
The host-as-slave controller operates in all system power states except MOFF. It may be used to generate interrupts
and resume events.
SMBALERT. The host controller includes support for the SMBALERT# signal. If this signal is asserted, then it is
expected that software determines the source by generating a host read cycle to the alert response address, 0001100b.
If the SMBus host controller detects this address for a read cycle with PME2[CYCTYPE] set to receive byte (001b),
then it stores the address returned by the SMBALERT# slave in PME6[7:0]. If bits[7:1] of this address are
1111_0xxb, indicating a 10-bit address, then it stores the next byte from the slave in PME6[15:8].
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