AMD-766 Datasheet, PDF (69/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
PM02: Power Management 1 Enable Register
IO mapped (base pointer: C3A58); offset: 03-02h. Default: 0000h. Read-write.
These bits work in conjunction with the corresponding bits in PM00 to generate SCI or SMI interrupts.
15:11
10
9
8
Reserved
RTC_EN
SLPBTN_EN PWRBTN_EN
7:6
5
4:1
0
Reserved
GBL_EN
Reserved
TMR_EN
TMR_EN. ACPI timer SCI enable. 1=Enable an SCI interrupt when PM00[TMR_STS] is set high. Note: This
results in an SCI interrupt, regardless as to the state of PM04[SCI_EN].
GBL_EN. Global SCI enable. 1=Enable an SCI interrupt when PM00[GBL_STS] is set high. Note: This results in
an SCI interrupt, regardless as to the state of PM04[SCI_EN].
PWRBTN_EN. Power button SCI/SMI enable. 1=Enable either an SCI or an SMI interrupt (based on the state of
PM04[SCI_EN]) when PM00[PWRBTN_STS] is set high.
SLPBTN_EN. Sleep button SCI/SMI enable. 1=Enable either an SCI or an SMI interrupt (based on the state of
PM04[SCI_EN]) when PM00[SLPBTN_STS] is set high.
RTC_EN. Real time clock alarm SCI/SMI enable. 1=Enable either an SCI or an SMI interrupt (based on the state
of PM04[SCI_EN]) when PM00[RTC_STS] is set high.
PM04: Power Management 1 Control Register
IO mapped (base pointer: C3A58); offset: 05-04h. Default: 0000h.
15:14
13
12:10
9:3
2
1
0
Reserved
SLP_EN SLP_TYP
Reserved
GBL_RLS BM_RLD SCI_EN
SCI_EN. SCI-SMI select. Read-write. Selects the type of interrupt generated by power management events.
0
SMI interrupt.
1
SCI interrupt.
Certain power management events may be programmed individually to generate SMI interrupts independent of the
state of this bit. Also, TMR_STS and GBL_STS always generate SCI interrupts regardless as to the state of this bit.
See section 4.6.1.1 for details.
BM_RLD. Bus master reload. Read-write. 1=Enables PM00[BM_STS] to resume from C3.
GBL_RLS. Global release. Read; write 1 to set; cleared by hardware. When this bit is set high, the hardware sets
PM28[BIOS_STS] high. GBL_RLS is cleared by the hardware when PM28[BIOS_STS] is cleared by software.
SLP_TYP. Sleep type. Read-write. Specifies the type of sleep state the system enters when SLP_EN is set high.
0 FON, S0. Full on.
1 POS, S1. Power on suspend.
2-4 Reserved.
5 STR, S3. Suspend to RAM.
6 STD, S4. Suspend to disk.
7 SOFF, S5. Soft off.
SLP_EN. Sleep enable. Write 1 only; reads back as 0. Writing a 1 to this bit causes the system to sequence into the
sleep state specified by SLP_TYP.
69