AMD-766 Datasheet, PDF (50/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
C1A08: EIDE Revision ID, Programming Interface, Sub Class and Base Registers
Configuration space; function 1; offset: 0B-08h. Default: 0101 8A01h.
31:24
23:16
15:8
7:0
BASE CLASS
SUB CLASS
PROG I/F[7:0]
REVISION ID
REVISION ID. Read only. EIDE controller silicon revision.
PROG I/F[0] Primary native mode. Read-write. 0=Compatibility mode for primary port; C1A10 and C1A14 are
ignored and not visible; address decode is based on legacy addresses 1F0-1F7h, 3F6h; C1A3C[7:0] read-only zeros;
C1A3C[15:8] = 00h; IRQ14 an ISA bus interrupt that may be used by the IDE controller. 1=native mode; C1A10
and C1A14 are visible and used for address decode; C1A3C[7:0] read-write; C1A3C[15:8] = 01h; IRQ14 pin
becomes NMPIRQ, used exclusively by the primary IDE port.
PROG I/F[1] Primary native/compatibility mode selectable. Read only. This is high to indicate that PROG
I/F[0] is read-write.
PROG I/F[2] Secondary native mode. Read-write. 0=compatibility mode for secondary port; C1A18 and C1A1C
are ignored and not visible; address decode is based on legacy addresses 170-177h, 376h; C1A3C[7:0] read-only
zeros; C1A3C[15:8] = 00h; IRQ15 an ISA bus interrupt that may be used by the IDE controller. 1=native mode;
C1A18 and C1A1C are visible and used for address decode; C1A3C[7:0] read-write; C1A3C[15:8] = 01h; IRQ15 pin
becomes NMSIRQ, used exclusively by the secondary IDE port.
PROG I/F[3] Secondary native/compatibility mode selectable. Read only. This is high to indicate that PROG
I/F[2] is read-write.
PROG I/F[6:4]. Read only. These bits are fixed in the low state.
PROG I/F[7] Master IDE Capability. Read only. This bit is fixed in the high state.
SUB CLASS[7:0]. Read only. These bits are fixed at 01h indicating an IDE controller.
BASE CLASS[7:0]. Read only. These bits are fixed at 01h indicating a mass storage device.
C1A0C: EIDE Controller BIST, Header and Latency Register
Configuration space; function 1; offset: 0F-0Ch. Default: 0000 0000h.
31:24
23:16
15:8
BIST
HEADER
LATENCY
CACHE. Read only. These bits are fixed at their default values.
LATENCY. Read-write. This field controls no hardware.
HEADER. Read only. These bits are fixed at their default values.
BIST. Read only. These bits are fixed at their default values.
7:0
CACHE
C1A10: EIDE Controller Primary Command Base Address
Configuration space; function 1; offset: 13-10h. Default: 0000 01F1h. Read-write. When C1A08[8] is low, the
primary port is in compatibility mode and this register is ignored and not visible (reads as 0h).
31:3
2:0
BASE
Reserved.
BASE[31:3] Port Address. These bits specify an 8-byte IO address space that maps to the ATA-compliant
command register set for the primary port (legacy IO space 1F0h through 1F7h).
C1A14: EIDE Controller Primary Control Base Address
Configuration space; function 1; offset: 17-14h. Default: 0000 03F5h. Read-write. When C1A08[8] is low, the
primary port is in compatibility mode and this register is ignored and not visible (reads as 0h).
31:2
1:0
BASE
Reserved.
BASE[31:2] Port Address. These bits specify a 4-byte IO address space that maps to the ATA-compliant control
register set for the primary port (legacy IO space 3F6h). Note: Only byte 2 of this space is used.
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