AMD-766 Datasheet, PDF (74/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
PBOR_DIS. Power button override disable. 1=The power button override event is disabled; PM00[PBOR_STS]
stays low and the system does not automatically transition to SOFF. 0=The power button override event is enabled.
SLPBTN_CTL. SLPBTN# resume. 1=Enables the assertion of PM00[SLPBTN_STS] to resume the system from
STR, STD, and SOFF.
SBOR_DIS. SLPBTN# override disable. 1=The sleep button override event is disabled; PM00[PBOR_STS] stays
low and the system does not automatically transition to SOFF. 0=The sleep button override event is enabled.
RI_CTL. RI# resume. 1=Enables the assertion of PM20[RI_STS] to resume the system from STR, STD, and SOFF.
PM28: Global Status Register
IO mapped (base pointer: C3A58); offset: 29-28h. Default: 0000h.
Each of the EVT bits in this register specify enabled status bits in other registers. These are not sticky bits; they
reflect the combinatorial equation of: _EVT = (status1 AND enable1) OR (status2 AND enable2)…
15
MISC_EVT
14
RI_STS
13
Reserved
12
Reserved
11
10
9
8
SMBUS_EVT THERM_STS EXTSMI_STS PME_STS
7
SWI_STS
6
BIOS_STS
5
SIT_STS
4
3
LPTUSB_EVT GPIO_EVT
2
PM1_EVT
1
TCO_EVT
0
TRP_EVT
TRP_EVT. Hardware trap status. Read only. 1=The enabled hardware trap status bits specified by PMA8 are
active.
TCO_EVT. TCO SMI interrupt event. Read only. 1=Any of PM44[NMI2SMI_STS, SW_TCO_SMI, TOUT_STS,
IBIOS_STS] are set.
PM1_EVT. Power management 1 status. Read only. 1=Any of the enabled power management events specified by
PM00 (enabled by PM02) are active.
GPIO_EVT. GPIO interrupt status. Read only. 1=Any of the enabled GPIO pin status bits specified by PMD4 are
active.
LPTUSB_EVT. LPT access or USB transfer or resume event status. Read only. 1=Any of the bits in PM24 that are
enabled in PM25 are active.
SIT_STS. System inactivity timer time out status. Access to this bit is replicated in PM20; see that register.
BIOS_STS. BIOS status. Read; set by hardware; write 1 to clear. 1=PM04[GBL_RLS] was set high. BIOS_STS is
cleared when a 1 is written to it; writing a 1 to BIOS_STS also causes the hardware to clear PM04[GBL_RLS]. This
bit may enabled to generate SMI interrupts only (if enabled in PM2A[BIOSSMI_EN]); it cannot be enabled to
generate SCI interrupts.
SWI_STS. Software SMI status. Read; set by hardware; write 1 to clear. 1=A write of any value was sent to PM2F
or PM1E. This bit may be enabled to generate SMI interrupts only (if enabled in PM2A[SWISMI_EN]); it cannot be
enabled to generate SCI interrupts.
PME_STS. PME# pin status. Access to this bit is replicated in PM20; see that register. This bit resides on the
VDD_AUX power plane.
EXTSMI_STS. External SMI pin status. Access to this bit is replicated in PM20; see that register. This bit resides
on the VDD_AUX power plane.
THERM_STS. THERM# pin status. Access to this bit is replicated in PM20; see that register.
SMBUS_EVT. System management bus status. Read only. 1=An SMBus event occurred including the completion
of the current SMBus host access, host-as-slave accesses, slave detect accesses, and assertion of SMBALERT#
(PME0 status bits enabled in PME2).
RI_STS. RI# pin status. Access to this bit is replicated in PM20; see that register. This bit resides on the
VDD_AUX power plane.
MISC_EVT. Miscellaneous SMI event. Read only. 1=Any of the status bits in PM30 that are enabled in PM32 are
active.
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