AMD-766 Datasheet, PDF (48/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
5.3.5 IOAPIC Registers
The IOAPIC register set for the 24 IOAPIC interrupts supported by the IC is indexed through two fixed-location,
memory-mapped ports: FEC0_0000h, which provides the 8-bit index register, and FEC0_0010h, which provides the
32-bit data port. Writes to the 32-bit data port at FEC0_0010h require that all four bytes be enabled.
The index register selects one of the following:
Index Description
Attribute
00h
APIC ID register. The ID is in bits[27:24]. All other bits are reserved.
Read-write
01h
IOAPIC version register.
Read only
02h
IOAPIC arbitration ID register. The ID is in bits[27:24]. All other bits Read only
are reserved.
10h-3Fh Redirection registers. Each of the 24 redirection registers uses two of these Read-write
indexes. Bits[63:32] are accessed through the odd indexes and bits[31:0] are
accessed through the even indexes.
40h-FFh Reserved.
Default
0000 0000h
0017 0011h
0000 0000h
0000 0000
0001 0000h
The redirection registers are defined as follows:
Bits Description
63:56 Destination. In physical mode, bits[59:56] specify the APIC ID of the target processor. In logical mode
bits[63:56] specify a set of processors.
55:17 Reserved.
16
Interrupt mask. 1=Interrupt is masked.
15
Trigger mode. 0=Edge sensitive. 1=Level sensitive.
14
IRR: interrupt request receipt. Read only. This bit is not defined for edge-triggered interrupts. For level-
triggered interrupts, this bit is set by the hardware after an interrupt is detected. It is cleared by receipt of
EOI with the vector specified in bits[7:0].
13
Polarity. 0=Active high. 1=Active low.
12
Delivery status. 0=Idle. 1=Interrupt message pending.
11
Destination mode. 0=Physical mode. 1=Logical mode.
10:8 Delivery mode. 000b=fixed. 001b=Lowest priority. 010b=SMI. 011b=Reserved. 100b=NMI. 101=Init.
110b=Reserved. 111b=ExtINT.
7:0 Interrupt vector.
5.3.6 Real-Time Clock Registers
RTC70: Real-Time Clock Legacy Indexed Address.
IO mapped (fixed); offset: 0070h. Default: 80h. Write only.
Note: RTC70[6:0] and RTC72 occupy the same physical register; after writes to RTC70, RTC72 reads back as {0b,
RTC70[6:0]}; after writes to RTC72, reads of RTC72 provide all 8 bits written.
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6:0
NMIDIS RTCADDR
RTCADDR. Real time clock address. Specifies the address of the real-time clock CMOS RAM. The data port
associated with this index is RTC71. Only the lower 128 bytes of the CMOS RAM are accessible through RTC70
and RTC71.
NMIDIS. NMI disable. 1=PORT61[IOCHK and SERR] are disabled from being able to generate NMI interrupts to
the processor. Note: The state of this register is read accessible through C0A41[NMIDIS].
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