AMD-766 Datasheet, PDF (18/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
4.3.4 Interrupt Controllers
The IC includes two interrupt controllers: the legacy PIC and an IOAPIC. Interrupt sources are routed to the
interrupt controllers as shown in the following diagram.
NMI, INIT
SMI
SCI
IRQ pins, TCO,
PNPIRQ[2:0],
serial IRQ
Interrupt
routing
logic
Interrupt pins APIC interrupt
to the host
message bus
Legacy
PIC ^INTR
PIRQ[D:A]#
24 IOAPIC
redirection
registers
GPIO[17, 16, 3, 2 ]
4.3.4.1 Interrupt Routing Logic
Vectored interrupt requests are routed to the legacy
PIC and APIC as shown. The interrupt signals to the
PIC may be either rising-edge triggered or active-low
level triggered. It is expected that edge-triggered
interrupts such as IRQ14 from the IDE controller rise
into the PIC to indicate the presence of an interrupt.
Conversely, level-sensitive interrupts are low into the
PIC to indicate the presence of an interrupt. Edge and
level sensitivity for each IRQ are programmed into the
PIC through PORT4D0.
USB_INT
PIRQ[D:A]#
PNPIRQ[2:0]
SCI_IRQ
IRQx (from ISA bus)
Serial IRQs
Interrupt
PORTD0
Routing _{PIC_IRQx PIC}
Logic
IOAPIC
The internal USB interrupt signal drives the PIRQD# pin low as an output; when the USB interrupt is deasserted,
PIRQD# is left in the high impedance state. So the USB interrupt is wired-ORed into the active state with external
interrupts on PIRQD#. The result enters the IC and goes to the interrupt routing logic.
The following are the interrupt routing logic equations:
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