AMD-766 Datasheet, PDF (43/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
PORTF0, PORTF1 and the FERR# and IGNNE# Logic
Fixed IO space; offset: F0h and F1h.
FERR# is used to control IGNNE# and
generate IRQ13 to the PIC and IOAPIC. The
diagram shows the logic. FERR_CLR# is
asserted by (1) an IO write to F0h, (2) an IO
write to F1h, (3) any processor reset command,
and (4) PWRGD reset; when any of these are
active, FERR_CLR# goes low.
FERR_CLR#
FERR#
GND
DQ
CLK
SET
IGNNE#
VDD
DQ
CLK
CLR
IRQ13
PORT4D0: Level Sensitive IRQ Select Register
Fixed IO space; offset: 4D1-4D0h. Default: 0000h. Read-write.
15:8
7:0
LIRQ1
LIRQ0
LIRQ0 and LIRQ1. Level sensitive IRQs. Each of these 16 bits controls whether a corresponding IRQ line that
enters the legacy PIC is edge sensitive (if the bit is low) or level sensitive (if it is high). Edge sensitive interrupts
must enter the PIC such that the rising edge generates the interrupt and level sensitive interrupts must enter the PIC
as active low; see section 4.3.4.1 for details about how the interrupts are mapped to the PIC. The bit numbers
correspond directly to the IRQ numbers (e.g., bit[12] controls IRQ12). Bits[0 and 2] are reserved (IRQ0 is always
edge sensitive and IRQ2 does not exist).
PORTCF9: Miscellaneous SMI Status Register
Fixed IO space; offset: CF9h. Default: 00h. Note: This register is enabled by C3A41[PCF9EN].
7
6
5
4
3
2
1
0
Reserved Reserved Reserved Reserved FULLRST RSTCMD SYSRST Reserved
SYSRST. System reset. Read-write. This bit specifies whether a full system reset or a processor INIT# interrupt is
generated when PORTCF9[RSTCMD] is written to a 1. 1=Full system reset with PCIRST# and CPURST# asserted
for 1.5 to 2.0 milliseconds. 0=INIT# asserted for 16 PCI clocks.
RSTCMD. Reset command. Write only; always reads as a zero. 1=A reset is generated as specified by bits[3,1] of
this register (bits[3,1] are observed in their state when RSTCMD is written to a 1; their previous value does not
matter).
FULLRST. Full reset. Read-write. 1=Full resets require the IC to place the system in the SOFF state for 3 to 5
seconds; full resets occurs whenever (1) RSTCMD and SYSRST are both written high, (2) an AC power fail is
detected (PWRGD goes low without the appropriate command), or (3) PM46[2NDTO_STS] is set while
C3A48[NO_REBOOT]=0. 0=Full resets do not transition the system to SOFF; only the reset signals are asserted.
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