AMD-766 Datasheet, PDF (30/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
4.6.4 Plug And Play
The IC supports three PNP IRQs and two PNP chip selects. The registers that specify these are C3A44 and C3A46.
The PNP pins are multiplexed with other functions. The control registers that specify the functions (the GPIO
control registers PM[D3:C0], PM[FF:F4]) must be set up appropriately for the PNP functions to operate.
4.6.5 General Purpose IO
The general-purpose IO pins, GPIO[31:0], may be assigned to be inputs, outputs, interrupt generators, or bus
controls. These pins may be programmed to be general-purpose IO or to serve alternate functions; see the PM[FF:F4,
D3:C0] register definitions. Many of these pins are named after their alternate functions. There is one control
register for each pin, PM[FF:F4, D3:C0]. IRQ status and enables are available for each pin in registers PMD4 and
PMD8.
General-purpose IO functions. When programmed as a GPIO pin, the following functions are available:
• Outputs.
- May be set high or low.
- May be controlled by GPIO output clocks 0 or 1 (see PMDC).
• Inputs.
- Active high or active low programmable.
- SCI or SMI IRQ capable.
- May be latched or not latched.
- Inputs may be debounce protected.
The following diagram shows the format for all GPIO pins. The input path is not disabled when the output path is
enabled or when the pin is used for an alternate function. In order for the latch to be set, the LE input must go high.
LTCH_STS
LATCH
To interrupt generator or 1
alternative logic ₀
Latch
QD
LE
DEBOUNCE
Vcc
1
0
Debounce
Circuit
ACTIVEHI
RTIN
1
0
Output
flip-flop
Pad
Input path
Output path
GPIO output
clocks 0 and 1
Output
mode
Debounce. The input signal must be active and stable for 12 to 16 milliseconds before the output signal is asserted.
GPIO output clocks. There are two GPIO output clocks (numbered 0 and 1). They are specified by PMDC. Each
output clock includes a 7-bit programmable high time, a 7-bit programmable low time, and the counter may be
clocked by one of four frequencies. Here are the options:
PMDC[CLK[1,0]BASE] Base clock period Output high time range
Output low time range
00b
250 microseconds 250 µs to 32 ms
250 us to 32 ms
01b
2 milliseconds 2 ms to 256 ms
2 ms to 256 ms
10b
16 milliseconds 16 ms to 2 seconds
16 ms to 2 seconds
11b
128 milliseconds 128 ms to 16.4 seconds
128 ms to 16.4 seconds
The output of the two GPIO output clocks may be selected to drive the output of any of the GPIO pins. They may be
used to blink LEDs or for other functions.
30