AMD-766 Datasheet, PDF (34/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
C0A40: ISA Bus Control 1 Register
Configuration space; function 0; offset: 40h Default: 00h Read-write.
7
6
5
4
3
2
1
0
Reserved Reserved Reserved LPC_IOR IORT
BLE
RWS
RWR
RWR. ROM write enable. 1=Write accesses to BIOS space specified by C0A43 are enabled. 0=BIOS write accesses
are disabled. This bit functions whether ROM space is located on the ISA bus or LPC bus. Note: Writing this bit
from 0 to 1 sets PM30[RWR_STS].
RWS. ROM wait states. 0=The ISA memory command signal (either MEMR# or MEMW#) is asserted for two
BCLK cycles when accessing BIOS on the ISA bus. 1=The ISA memory command signal is asserted for one BCLK
cycle when accessing BIOS on the ISA bus. If C3A48[ISABIOS]=0, then this bit has no affect.
BLE. BIOS lock enable. Read; write 1 only. 1=Setting C0A40[RWR] from 0 to 1 sets PM44[IBIOS_STS] and
generate an SMI. 0=Setting C0A40[RWR] from 0 to 1 does not set PM44[IBIOS_STS] and does not generate an
SMI. Once this BLE is set, it can only be cleared by PCIRST#.
IORT. IO recovery time. 0=There are a minimum of 5.5 BCLK cycles between the trailing edge of an ISA IO
command signal (IOR# or IOW#) and the leading edge of the ISA IO command signal for the subsequent ISA bus IO
cycle and there are at least 22 PCLKs between LPC IO cycles. 1=There are a minimum of 13.5 BCLK cycles
between adjacent ISA bus IO cycles and there are at least 54 PCLKs between LPC IO cycles. This bit does not affect
memory cycles.
LPC_IOR. LPC IO recovery. 1= IO recovery delay (specified by IORT) enforced for both LPC and legacy IO
cycles. 0=IO recovery delay only enforced for legacy IO cycles (cycles to the DMA controller, legacy PIC,
programmable interval timer, and real-time clock).
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