AMD-766 Datasheet, PDF (10/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
Pin name and description
reset signal from the system keyboard controller. When asserted, an INIT
interrupt to the processor is generated.
LA[23:17]. ISA system address bus bits[23:17]. LA[23:17] and SA[16:0]
combine to for the 24-bit ISA address bus.
LAD[3:0]. LPC address-data bus.
LDRQ0# and LDRQ1#. LPC DMA request signals.
LFRAME#. LPC frame signal.
MEMR#. ISA bus memory cycle read command.
MEMW#. ISA bus memory cycle write command.
OSC. 14.31818 MHz. clock. This is used for the programmable interval
timer and various power management timers.
ROM_KBCS#. ROM chip select and keyboard chip select. This is
designed to be connected to both the ISA-bus system ROM BIOS and the
keyboard controller. During ISA bus memory accesses this pin decodes
ROM BIOS memory space, as defined by C0A43 (if the ISABIOS pin is
high). During ISA bus IO cycles to the legacy keyboard controller, this
pin decodes accesses to the keyboard controller. The state of this bit is
captured during reset in C3A48[3].
SA[16:0]. ISA system address bus bits[16:0]. LA[23:17] and SA[16:0]
combine to for the 24-bit ISA address bus.
SD[7:0]. ISA data bus.
SPKR. Speaker driver from the programmable interval timer. This pin is
an input while PWRGD is low; it is used to select the default state of
C3A48[ENIDE, ENPCI, ENISA] (the internal pull-up-pull-down IO pin
resister enables).
IO cell
type
Output
IO
Input
IO
Output
Output
Input
IO
Output
IO-PU
IO
Power
plane
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
During
Reset
Low
3-state
-
High
High
High
-
Input
Low
3-state
Input
Post
Reset
Low
3-state
-
High
High
High
-
High
Low
3-state
Low
POS
Last
state
3-state
-
High
High
High
-
High
Last
state
3-state
Last
state
3.5 Ultra DMA Enhanced IDE Interface
Pin name and description
IO cell
type
DADDR[P,S][2:0]. IDE controller [primary, secondary] port address. Output
DCS1P#. IDE controller primary port chip select 1. This is active during Output
accesses to the IO address space 1F7h – 1F0h.
DCS1S#. IDE controller secondary port chip select 1. This is active
Output
during accesses to the IO address space 177h – 170h.
DCS3P#. IDE controller primary port chip select 3. This is active during Output
accesses to the IO address space 3F7h – 3F4h.
DCS3S#. IDE controller secondary port chip select 3. This is active
Output
during accesses to the IO address space 377h – 374h.
DDACK[P,S]#. IDE controller [primary, secondary] port DMA
Output
acknowledge signal.
DDATA[P,S][15:0]. IO; IDE controller [primary, secondary] port data
IO
bus.
DDRQ[P,S]. Input; IDE controller [primary, secondary] port DMA
Input-
request signal.
PD
DIOR[P,S]#. Output; IDE controller [primary, secondary] port IO read Output
command.
DIOW[P,S]#. Output; IDE controller [primary, secondary] port IO write Output
command.
DRDY[P,S]. Input; IDE controller [primary, secondary] port ready strobe. Input
Power
plane
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
During
Reset
Low
High
High
High
High
High
3-state
-
High
High
-
Post
Reset
Low
High
High
High
High
High
3-state
-
High
High
-
POS
Low
High
High
High
High
High
3-state
-
High
High
-
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